View MSC8122MP8000_2504355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor technical data msc8122 rev. 13, 10/2006 ? freescale semiconductor, inc., 2004, 2006. all rights reserved. msc8122 quad core 16-bit digital signal processor the msc8122 is a highly integrated system-on-a-chip that combines four sc140 extended cores with an rs-232 serial interface, four time-division multiplexed (tdm) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (siu), an ethernet interface, and a multi-channel dma engine. the four extended cores can deliver a total 4800/6400/8000 dsp mmacs performance at 300/400/500 mhz. each core has four arithmetic logic units (alus), internal memory, a write buffer, and two interrupt controllers. the msc8122 targets high-bandwidth highly computational dsp applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. the msc8122 delivers enhanced performance while maintaining low power dissipation and greatly reducing system cost. figure 1. msc8122 block diagram mqbus sqbus local bus 128 128 boot rom 64 pll jtag rs-232 internal local bus internal system bus ipbus ip master 64 64 uart memory controller m2 ram gpio pins interrupts memory controller system bus 32/64 dsi port 32 32/64 pll/clock jtag port sc140 extended core sc140 extended core sc140 extended core system interface 32 timers 4 tdms sc140 extended core dma bridge siu registers direct slave interface (dsi) 8 hardware semaphores gic gpio mii/rmii/smii ethernet the raw processing power of this highly integrated system- on- a-chip device will enable developers to create next- generation networking products that offer tremendous channel densities, while maintaining system flexibility, scalability, and upgradeability. the msc8122 is offered in three core speed levels: 300, 400, and 500 mhz. what?s new? rev. 13 includes the following: ?chapter 2 updates table 2-13 to add timings 17 and 18 for irqs.
msc8122 technical data, rev. 13 ii freescale semiconductor table of contents table of contents features....................................................................................................................... ........................................iv product documentation .......................................................................................................... ............................ix chapter 1 signals/connections 1.1 power signals ............................................................................................................... ....................................1-3 1.2 clock signals ............................................................................................................... .....................................1-3 1.3 reset and configuration signals............................................................................................. ..........................1-3 1.4 direct slave interface, system bus, ethernet, and interrupt signals ......................................................... ......1-4 1.5 memory controller signals ................................................................................................... .........................1-14 1.6 gpio, tdm, uart, and timer signals.......................................................................................... ...............1-16 1.7 dedicated ethernet signals.................................................................................................. ...........................1-23 1.8 eonce event and jtag test access port signals ............................................................................... .........1-24 1.9 reserved signals............................................................................................................ .................................1-24 chapter 2 specifications 2.1 maximum ratings............................................................................................................. ................................2-1 2.2 recommended operating conditions............................................................................................ ...................2-2 2.3 thermal characteristics ..................................................................................................... ...............................2-3 2.4 dc electrical characteristics............................................................................................... .............................2-3 2.5 ac timings.................................................................................................................. .....................................2-4 chapter 3 packaging 3.1 package description ......................................................................................................... ................................3-1 3.2 msc8122 package mechanical drawing .......................................................................................... .............3-20 chapter 4 design considerations 4.1 start-up sequencing recommendations ......................................................................................... ..................4-1 4.2 power supply design considerations.......................................................................................... .....................4-1 4.3 connectivity guidelines ..................................................................................................... ..............................4-3 4.4 external sdram selection.................................................................................................... ..........................4-4 4.5 thermal considerations...................................................................................................... ..............................4-5 data sheet conventions overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il / v ol pin false deasserted v ih / v oh pin true asserted v ih / v oh pin false deasserted v il / v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications.
data sheet conventions msc8122 technical data, rev. 13 freescale semiconductor iii figure 2. sc140 extended core block diagram sc140 power management core program sequencer address register file data alu register file address alu data alu eonce jtag xa xb p qbus irqs irqs mqbus sqbus local bus 128 128 64 64 64 lic pic 128 128 sc140 core qbus interface instruction cache m1 ram notes: 1. the arrows show the data transfer direction. qbus bank 1 qbus bank 3 2 . the qbus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four qbus banks. in addition, the qbc handles internal qbc memory contentions.
msc8122 technical data, rev. 13 iv freescale semiconductor features features feature description sc140 cores four sc140 cores: ? up to 8000 mmacs using 16 alus running at up to 500 mhz. ? a total of 1436 kb of internal sram (224 kb per core + 16 kb icache per core + the shared m2 memory). each sc140 core provides the following: ? up to 2000 mmacs using an internal 500 mhz clock. a mac operation includes a multiply-accumulate command with the associated data move and pointer update. ? 4 alus per sc140 core. ? 16 data registers, 40 bits each. ? 27 address registers, 32 bits each. ? hardware support for fracti onal and integer data types. ? very rich 16-bit wide orthogonal instruction set. ? up to six instructions executed in a single clock cycle. ? variable-length execution set (vles) that can be optimized for code density and performance. ? ieee std 1149.1? jtag port. ? enhanced on-device emulation (eonce) with real-time debugging capabilities. extended core each sc140 core is embedded within an extended core that provides the following: ? 224 kb m1 memory that is accessed by the sc140 core with zero wait states. ? support for atomic accesses to the m1 memory. ? 16 kb instruction cache, 16 ways. ? a four-entry write buffer that frees the sc140 core from waiting for a write access to finish. ? external cache support by asserting the global si gnal (gbl) when predefined memory banks are accessed. ? programmable interrupt controller (pic). ? local interrupt controller (lic). multi-core shared memories ? 476 kb m2 memory (shared memory) working at the core frequency, accessible from the local bus, and accessible from all four sc140 cores using the mqbus. ? 4 kb bootstrap rom. m2-accessible multi- core bus (mqbus) ? a qbus protocol multi-master bus connecting the four sc140 cores to the m2 memory. ? data bus access of up to 128-bit read and up to 64-bit write. ? operation at the sc140 core frequency. ? a central efficient round-robin arbiter controlling sc140 core access on the mqbus. ? atomic operation control of access to m2 memory by the four sc140 cores and the local bus. internal pll ? generates up to 500 mhz core clock and up to166 mhz bus clocks for the 60x-compatible local and system buses and other modules. ? pll values are determined at reset based on configuration signal values. 60x-compatible system bus ? 64/32-bit data and 32-bit address 60x bus. ? support for multiple-master designs. ? four-beat burst transfers (eight-beat in 32-bit wide mode). ? port size of 64, 32, 16, and 8 controlled by the internal memory controller. ? bus can access external memory expans ion or off-device peripherals, or it can enable an external host device to access internal resources. ? slave support, direct access by an external host to internal resources including the m1 and m2 memories. ? on-device arbitration between up to four master devices. direct slave interface (dsi) a 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host processor. ? 21?25 bit address, 32/64-bit data. ? direct access by an external host to internal and exter nal resources, including the m1 and the m2 memories as well as external devices on the system bus. ? synchronous and asynchronous accesses, with burst capability in the synchronous mode. ? dual or single strobe modes. ? write and read buffers improve host bandwidth. ? byte enable signals enables 1, 2, 4, and 8 byte write access granularity. ? sliding window mode enables access wi th reduced number of address pins. ? chip id decoding enables using one cs signal for multiple dsps. ? broadcast cs signal enables parallel write to multiple dsps. ? big-endian, little-endian, and munged little-endian support. 3-mode signal multiplexing ? 64-bit dsi, 32-bit system bus. ? 32-bit dsi, 64-bit system bus. ? 32-bit dsi, 32-bit system bus.
features msc8122 technical data, rev. 13 freescale semiconductor v memory controller flexible eight-bank memory controller: ? three user-programmable machi nes (upms), general-purpose chip-select machine (gpcm), and a page-mode sdram machine. ? glueless interface to sram, page mode sdram, dram , eprom, flash memory, and other user-definable peripherals. ? byte enables for either 64-bit or 32-bit bus width mode. ? eight external memory banks (banks 0?7). two addi tional memory banks (banks 9, 11) control ipbus peripherals and internal memories. each bank has the following features: ? 32-bit address decoding with programmable mask. ? variable block sizes (32 kb to 4 gb). ? selectable memory controller machine. ? two types of data errors check/correction: normal odd/even parity and read-modify-write (rmw) odd/even parity for single accesses. ? write-protection capability. ? control signal generation machine selection on a per-bank basis. ? support for internal or external masters on the system bus. ? data buffer controls activated on a per-bank basis. ? atomic operation. ? rmw data parity check (on system bus only). ? extensive external memory-controller/bus-slave support. ? parity byte select pin, which enables a fast, gluele ss connection to rmw-parity devices (on the system bus only). ? data pipeline to reduce data set-up time for synchronous devices. multi-channel dma controller ? 16 time-multiplexed unidirectional channels. ? services up to four external peripherals. ? supports done or drack protocol on two external peripherals. ? each channel group services 16 inter nal requests generated by eight internal fifos. each fifo generates: ? a watermark request to indicate that the fifo contains data for the dma to empty and write to the destination. ? a hungry request to indicate that the fifo can accept more data. ? priority-based time-multiplexing between c hannels using 16 internal priority levels. ? round-robin time-multiplexing between channels. ? a flexible channel configuration: ? all channels support all features. ? all channels connect to the system bus or local bus. ? flyby transfers in which a single data access is transfe rred directly from the source to the destination without using a dma fifo. time-division multiplexing (tdm) up to four independent tdm modules, each with the following features: ? optional operating configurations: ? totally independent receive and transmit channels, each having one data line, one clock line, and one frame sync line. ? four data lines with one clock and one frame sync shared among the transmit and receive lines. ? connects gluelessly to most t1/e1 framers as well as to common buses such as the st-bus. ? hardware a-law/ -law conversion. ? up to 62.5 mbps per tdm (62.5 mhz bit clock if one data line is used, 31.25 mhz if two data lines are used, 15.63 mhz if four data lines are used). ? up to 256 channels. ? up to 16 mb per channel buffer (granularity 8 bytes), where a/ law buffer size is double (granularity 16 byte). ? receive buffers share one global write of fset pointer that is written to the same offset relative to their start address. ? transmit buffers share one global read offset pointer that is read from the same offset relative to their start address. ? all channels share the same word size. ? two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering. ? each channel can be programmed to be active or inactive. ? 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively. ? the tdm transmitter sync signal (txtsyn) can be configured as either input or output. ? frame sync and data signals can be programmed to be sa mpled either on the rising edge or on the falling edge of the clock. ? frame sync can be programmed as active low or active high. ? selectable delay (0?3 bits) between the fram e sync signal and the beginning of the frame. ? msb or lsb first support. feature description
msc8122 technical data, rev. 13 vi freescale semiconductor features ethernet controller ? designed to comply with ieee ? std 802? including std. 802.3?, 802.3u?, 802.3x?, and 802.3ac?. ? three ethernet physical interfaces: ? 10/100 mbps mii. ? 10/100 mbps rmii. ? 10/100 mbps smii. ? full and half-duplex support. ? full-duplex flow control (automatic pause frame gener ation or software programmed pause frame generation and recognition). ? out-of-sequence transmit queue for initiating flow-control. ? programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (vlan) tags and priority. ? retransmission from transmit fifo following a collision. ? crc generation and verification of inbound/outbound packets. ? address recognition: ? each exact match can be programm ed to be accepted or rejected. ? broadcast address (accept/reject). ? exact match 48-bit individual (unicast) address. ? hash (256-bit hash) check of individual (unicast) addresses. ? hash (256-bit hash) check of group (multicast) addresses. ? promiscuous mode. ? pattern matching: ? up to 16 unique 4-byte patterns. ? pattern match on bit-basis. ? matching range up to 256 bytes deep into the frame. ? offsets to a maximum of 252 bytes. ? programmable pattern size in 4-byte increments up to 64 bytes. ? accept or reject frames if a match is detected. ? up to eight unicast addresses for exact matches. ? pattern matching accepts/rejects ip addresses. ? filing of receive frames based on pattern match; prioritization of frames. ? insertion with expansion or replacement for transmit frames; vlan tag insertion. ? rmon statistics. ? master dma on the local bus for fetching descriptors and accessing the buffers. ? ethernet phy can be exposed either on gpio pins or on the high most significant bits of the dsi/system when the dsi and the system bus are both 32 bits. ? mpc8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode. ? mii bridge (miigsk): ? programmable selection of the 50 mhz rmii re ference clock source (external or internal). ? independent 2 bit wide transmit and receive data paths. ? six operating modes. ? four general-purpose control signals. ? programmable transmitted inter-frame bits to support inter-frame gap for frames in the smii domain. ? smii features: ? multiplexed only with gpio signals ? convey complete mii information between the phy and mac. ? allow direct mac-to-mac communication in smii mode. ? can generate an interrupt request line while receiving inter-frame segments. feature description
features msc8122 technical data, rev. 13 freescale semiconductor vii uart ? two signals for transmit data and receive data. ? no clock, asynchronous mode. ? can be serviced either by the sc140 dsp cores or an external host on the system bus or the dsi. ? full-duplex operation. ? standard mark/space non-return-to-zero (nrz) format. ? 13-bit baud rate selection. ? programmable 8-bit or 9-bit data format. ? separately enabled transmitter and receiver. ? programmable transmitter output polarity. ? two receiver wake-up methods: ? idle line wake-up. ? address mark wake-up. ? separate receiver and transmitter interrupt requests. ? nine flags, the first five can generate interrupt request: ? transmitter empty. ? transmission complete. ? receiver full. ? idle receiver input. ? receiver overrun. ? receiver active. ? noise error. ? framing error. ? parity error. ? receiver framing error detection. ? hardware parity checking. ? 1/16 bit-time noise detection. ? maximum bit rate 6.25 mbps. ? single-wire and loop operations. general-purpose i/o (gpio) port ? 32 bidirectional signal lines that either serve the peripherals or act as programmable i/o ports. ? each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode. i 2 c software module ? booting from a serial eeprom. ? uses gpio timing. timers two modules of 16 timers each. ? cyclic or one-shot. ? input clock polarity control. ? interrupt request when counting reaches a programmed threshold. ? pulse or level interrupts. ? dynamically updated programmed threshold. ? read counter any time. watchdog mode for the timers that connect to the device. hardware semaphores eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism. global interrupt controller (gic) ? consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to int_out , nmi_out , and to the cores. ? generation of 32 virtual interrupts (eight to each sc140 core) by a simple write access. ? generation of virtual nmi (one to each sc140 core) by a simple write access. reduced power dissipation ? low power cmos design. ? separate power supply for internal logic (1.2 v or 1.1 v) and i/o (3.3 v). ? low-power standby modes. ? optimized power management circuitry (ins truction-dependent, peripheral-dependent, and mode-dependent). packaging ? 0.8 mm pitch flip-chip plastic ball-grid arra y (fc-pbga) with lead-free or lead-bearing spheres. ? 431-connection (ball). ?20 mm 20 mm. real-time operating system (rtos) the real-time operating system (rtos) fully supports device architecture (multi-core, memory hierarchy, icache, timers, dma controller, interrupts, peripherals), as follows: ? high-performance and deterministic, delivering predictive response time. ? optimized to provide low interrupt latency with high data throughput. ? preemptive and priori ty-based multitasking. ? fully interrupt/event driven. ? small memory footprint. ? comprehensive set of apis. feature description
msc8122 technical data, rev. 13 viii freescale semiconductor features multi-core support ? one instance of kernel code in all four sc140 cores. ? dynamic and static memory allocation from local memory (m1) and shared memory (m2). distributed system support enables transparent inter-task communications between tasks running inside the sc140 cores and the other tasks running in on-board devices or remote network devices: ? messaging mechanism between tas ks using mailboxes and semaphores. ? networking support; data transfer between tasks running inside and outside the device using networking protocols. ? includes integrated device drivers for such peripherals as tdm, uart, and external buses. software support ? task debugging utilities integrated with compilers and vendors. ? board support package (bsp) for the application development system (ads). ? integrated development environment (ide): ? c/c++ compiler with in-line assembly so developer s can generate highly optimized dsp code. translates c/c++ code into parallel fetch sets and maintains high code density. ? librarian. user can creat e libraries for modularity. ? a collection of c/c++ functions for developer use. ? highly efficient linker to produce executables from object code. ? seamlessly integrated real-time, non-intrusiv e multi-mode debugger for debugging highly optimized dsp algorithms. the developer can choose to debug in source code, assembly code, or mixed mode. ? device simulation models enable design and simulation before hardware availability. ? profiler using a patented binary code instrumentati on (bci) technique helps developers identify program design inefficiencies. ? version control. metrowerks? codewarrior? includes plug-ins for clearcase, visual sourcesafe, and cvs. boot options ? external memory. ? external host. ?uart. ?tdm. ?i 2 c msc8122ads ? host debug through single jtag connector supports both processors. ? msc8103 as the msc8122 host with both devices on t he board. the msc8103 system bus connects to the msc8122 dsi. ? flash memory for stand-alone applications. ? communications ports: ? 10/100base-t. ? 155 mbit atm over optical. ? t1/e1 tdm interface. ? h.110. ? voice codec. ? rs-232. ? high-density (mictor) logic analyzer connectors to monitor msc8122 signals ? 6u compactpci form factor. ? emulates msc8122 dsp farm by connecting to three other ads boards. feature description
product documentation msc8122 technical data, rev. 13 freescale semiconductor ix product documentation the documents listed in table 1 are required for a complete description of the msc8122 and are necessary to design properly with the part. documentation is available from a local freescale distributor, a freescale semiconductor sales office, or a freescale literature distribution center. for documentation updates, visit the freescale dsp website. see the contact information on the back of this document. table 1. msc8122 documentation name description order number msc8122 technical data msc8122 features list and physical, elec trical, timing, and package specifications msc8122 msc8122 user?s guide user information includes system functi onality, getting started, and programming topics availability tbd msc8122 reference manual detailed functional description of the msc8122 memory and peripheral configuration, operation, and register programming msc8122rm starcore? sc140 dsp core reference manual detailed description of the sc140 family processor core and instruction set mnsc140core application notes documents describing specific applicati ons or optimized devic e operation including code examples refer to the msc8122 product page.
msc8122 technical data, rev. 13 x freescale semiconductor
msc8122 technical data, rev. 13 freescale semiconductor 1-1 signals/connections 1 the msc8122 external signals are organized into functional groups, as shown in table 1-1 and figure 1-1 . ta b l e 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group. figure 1-1 shows msc8122 external signals organized by function. table 1-1. msc8122 functional signal groupings functional group number of signal connections description power (v dd , v cc , and gnd) 155 table 1-2 on page 1-3 clock 3 table 1-3 on page 1-3 reset and configuration 4 table 1-4 on page 1-3 dsi, system bus, ethernet, and interrupts 210 table 1-5 on page 1-4 memory controller 16 table 1-6 on page 1-14 general-purpose input/output (gpio), time-d ivision multiplexed (tdm) interface, universal asynchronous receiver/ trans mitter (uart), ethernet, and timers 32 table 1-7 on page 1-16 dedicated ethernet signals 3 table 1-8 on page 1-23 eonce and jtag test access port 7 table 1-9 on page 1-24 reserved (denotes connections that are always reserved) 1 table 1-10 on page 1-24
msc8122 technical data, rev. 13 1-2 freescale semiconductor signals/connections hd0/swte ? 1 d s i / s y s. b u s / e t h e r n e t s y s t e m b u s 32 ? a[0?31] hd1/dsisync ? 1 1 ? tt0/ha7 hd2/dsi64 ? 1 1 ? tt1 hd3/modck1 ? 1 3 ? tt[2?4]/ cs[5?7] hd4/modck2 ? 1 5 cs[0?4] hd5/cnfgs ? 1 4 ? tsz[0?3] hd[6?31] ? 26 1 ? tbst hd[32-39]/d[32-39]/reserved ? 8 1 ? irq1 / gbl hd40/d40/ethrxd0 ? 1 1 ? irq3 /baddr31 hd41/d41/ethrxd1 ? 1 1 ? irq2 /baddr30 hd42/d42/ethrxd2/reserved ? 1 1 ? irq5 /baddr29 hd43/d43/ethrxd3/reserved ? 1 1 baddr28 hd[44-45]/d[44-45]/reserved ? 2 1 baddr27 hd46/d46/ethtxd0 ? 1 1 ? br hd47/d47/ethtxd1 ? 1 1 ? bg hd48/d48/ethtxd2/reserved ? 1 1 ? dbg hd49/d49/ethtxd3/reserved ? 1 1 ? abb / irq4 hd[50-53]/d[50-53]/reserved ? 4 1 ? dbb / irq5 hd54/d54/ethtx_en ? 1 1 ? ts hd55/d55/ethtx_er/reserved ? 1 1 ? aack hd56/d56/ethrx_dv/ethcrs_dv ? 1 1 ? artry hd57/d57/ethrx_er ? 1 32 ? d[0?31] hd58/d58/ethmdc ? 1 1 ? reserved/dp0/dreq1/ ext_br2 hd59/d59/ethmdio ? 1 1 ? irq1 /dp1/ dack1 / ext_bg2 hd60/d60/ethcol/reserved ? 1 1 ? irq2 /dp2/ dack2 / ext_dbg2 hd[61?63]/d[61-63]/reserved ? 3 1 ? irq3 /dp3/dreq2/ ext_br3 hcid[0?2] 3 m e m c d s i 1 ? irq4 /dp4/ dack3 / ext_dbg3 hcid3/ha8 1 1 ? irq5 /dp5/ dac k4 / ext_bg3 ha[11?29] 19 1 ? irq6 /dp6/dreq3 hwb s[0?3] / hdbs [0?3] / hwb e[0?3] / hdb e[0?3] 4 1 ? irq7 /dp7/dreq4 hwb s[4?7] / hdb s[4?7 ]/ hw be[4?7] / hdbe [4?7 ]/ pw e[4?7] / psdd qm[4?7 ]/ pb s[4?7] ? 4 1 ? ta hrds /hrw/ hrde 1 1 ? tea hbrst 1 1 nmi hdst[0?1]/ha[9?10] 2 1 nmi_out hcs 1 1 ? psdval hbcs 1 1 ? irq7 / int_out hta 1 m e m c s y s 1 bctl0 hclkin 1 1 bctl1 / cs 5 gpio0/chip_id0/ irq4 /ethtxd0 ? 1 g p i o / t d m / e t h e r n e t / t i m e r s / i 2 c 3 ? bm[0?2]/tc[0?2]/bnksel[0?2] gpio1/timer0/chip_id1/ irq5 /ethtxd1 ? 1 1 ale gpio2/timer1/chip_id2/ irq6 ? 1 4 pwe[0?3] / psddqm [0?3] / pbs [0?3] gpio3/tdm3tsyn/ irq1/ ethtxd2 ? 1 1 psda10/pgpl0 gpio4/tdm3tclk/ irq2/ ethtx_er ? 1 1 psdwe /pgpl1 gpio5/tdm3tdat/ irq3/ ethrxd3 ? 1 1 poe / psdras/ pgpl2 gpio6/tdm3rsyn/ irq4/ ethrxd2 ? 1 1 psdcas /pgpl3 gpio7/tdm3rclk/ irq5/ ethtxd3 ? 1 1 ? pgta /pupmwait/pgpl4/ ppbs gpio8/tdm3rdat/ irq6/ ethcol ? 1 1 psdamux/pgpl5 gpio9/tdm2tsyn/ irq7/ ethmdio ? 1 gpio10/tdm2tclk/ irq8/ ethrx_dv/ethcrs_dv/nc ? 1 de bug 1 ee0 gpio11/tdm2tdat/ irq9/ ethrx_er/ethtxd ? 1 1 ee1 gpio12/tdm2rsyn/ irq10/ ethrxd1/ethsync ? 1 c l k 1 clkout gpio13/tdm2rclk/ irq11/ ethmdc ? 1 1 reserved gpio14/tdm2rdat/ irq12/ ethrxd0/nc ? 1 1 clkin gpio15/tdm1tsyn/dreq1 ? 1 r e s e t 1 poreset gpio16/tdm1tclk/ done1/drack1 ? 1 1 ? hreset gpio17/tdm1tdat/ dack1 ? 1 1 ? sreset gpio18/tdm1rsyn/dreq2 ? 1 1 rstconf gpio19/tdm1rclk/ dack2 ? 1 j t a g 1 tms gpio20/tdm1rdat ? 1 1 tdi gpio21/tdm0tsyn ? 1 1 tck gpio22/tdm0tclk/ done2 / drack2 ? 1 1 trst gpio23/tdm0tdat/ irq13 ? 1 1 tdo gpio24/tdm0rsyn/ irq14 ? 1 gpio25/tdm0rclk/ irq15 ? 1 gpio26/tdm0rdat ? 1 gpio27/urxd/dreq1 ? 1 gpio28/utxd/dreq2 ? 1 gpio29/chip_id3/ethtx_en ? 1 ded. eth. net 1 ethrx_clk/ethsync_in gpio30/timer2/tmclk/sda ? 1 1 ethtx_clk/ethref_clk/ethclock gpio31 / timer3/scl ? 1 1 ethcrs/ethrxd power signals are: v dd , v ddh , v ccsyn , gnd, gnd h , and gnd syn . reserved signals can be left unconnected. nc signals must not be connected. figure 1-1. msc8122 external signals
power signals msc8122 technical data, rev. 13 freescale semiconductor 1-3 1.1 power signals 1.2 clock signals 1.3 reset and configuration signals table 1-2. power and ground signal inputs signal name description v dd internal logic power v dd dedicated for use with the device core. the voltage s hould be well-regulated and the input should be provided with an extremely low impedance path to the v dd power rail. v ddh input/output power this source supplies power for the i/o buffers. the user must provide adequate exte rnal decoupling capacitors. v ccsyn system pll power v cc dedicated for use with the system phase lock loop (pll). the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. gnd system ground an isolated ground for the internal processing logic and i/o buf fers. this connection must be tied externally to all chip ground connections, except gnd syn . the user must provide adequate external decoupling capacitors. gnd syn system pll ground ground dedicated for system pll use. the connection shoul d be provided with an extremel y low-impedance path to ground. table 1-3. clock signals signal name type signal description clkin input clock in primary clock input to the msc8122 pll. clkout output clock out the bus clock. reserved input reserved. pull down to ground. table 1-4. reset and configuration signals signal name type signal description poreset input power-on reset when asserted, this line causes the msc8122 to enter power-on reset state. rstconf input reset configuration used during reset configuration sequence of the chip. a detailed explanation of its function is provided in the msc8122 reference manual . this signal is sampled upon deassertion of poreset . note: when poreset is deasserted, the msc8122 also samples the following signals: ? bm[0?2]?selects the boot mode. ? modck[1?2]?selects the clock configuration. ? swte?enables the software watchdog timer. ? dsisync, dsi64, cnfgs, and chip_id[0?3]?configures the dsi. refer to table 1-5 for details on these signals. hreset input/output hard reset when asserted as an input, this signal causes the msc8122 to enter hard reset state. after the device enters a hard reset state, it drives the signal as an open-drain output. sreset input/output soft reset when asserted as an input, this signal causes the msc8122 to enter soft reset state. after the device enters a soft reset state, it drives the signal as an open-drain output.
msc8122 technical data, rev. 13 1-4 freescale semiconductor signals/connections 1.4 direct slave interface, system bus, ethernet, and interrupt signals the direct slave interface (dsi) is combined with the system bus because they share some common signal lines. individual assignment of a signal to a specific signal line is configured through internal registers. table 1-5 describes the signals in this group. note: although there are fifteen interrupt request (irq) connections to the core processors, there are multiple external lines that can connect to these internal signal lines. after reset, the default configuration enables only irq[1?7] , but includes two input lines each for irq[1?3] and irq7 . the designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. additional alternate irq lines and irq[8?15] are enabled through the gpio signal lines. table 1-5. dsi, system bus, ethernet, and interrupt signals signal name type description hd0 swte input/ output input host data bus 0 bit 0 of the dsi data bus. software watchdog timer disable . it is sampled on the rising edge of poreset signal. hd1 dsisync input/ output input host data bus 1 bit 1 of the dsi data bus. dsi synchronous distinguishes between synchronous and as ynchronous operation of the dsi. it is sampled on the rising edge of poreset signal. hd2 dsi64 input/ output input host data bus 2 bit 2 of the dsi data bus. dsi 64 defines the width of the dsi and system data buses. it is sampled on the rising edge of poreset signal. hd3 modck1 input/ output input host data bus 3 bit 3 of the dsi data bus. clock mode 1 defines the clock frequencies. it is sampled on the rising edge of poreset signal. hd4 modck2 input/ output input host data bus 4 bit 4 of the dsi data bus. clock mode 2 defines the clock frequencies. it is sampled on the rising edge of poreset signal. hd5 cnfgs input/ output input host data bus 5 bit 5 of the dsi data bus. configuration source one signal out of two that indicates reset configuration mode. it is sampled on the rising edge of poreset signal. hd[6?31] input/ output host data bus 6?31 bits 6?31 of the dsi data bus.
direct slave interface, system bus, ethernet, and interrupt signals msc8122 technical data, rev. 13 freescale semiconductor 1-5 hd[32?39 ] d[32?39] reserved input/ output input/ output input host data bus 32?39 bits 32?39 of the dsi data bus. system bus data 32?39 for write transactions, the bus master drives valid data on this bus. for read transactions, the slave drives valid data on this bus. if the ethernet port is enabled and multiplexed with t he dsi/system bus, these pins are reserved and can be left unconnected. hd40 d40 ethrxd0 input/ output input/ output input host data bus 40 bit 40 of the dsi data bus. system bus data 40 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data 0 in mii and rmii modes, bit 0 of the ethernet receive data. hd41 d41 ethrxd1 input/ output input/ output input host data bus 41 bit 41 of the dsi data bus. system bus data 41 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data 1 in mii and rmii modes, bit 1 of the ethernet receive data. hd42 d42 ethrxd2 reserved input/ output input/ output input input host data bus 42 bit 42 of the dsi data bus. system bus data 42 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data 2 in mii mode only, bit 2 of the ethernet receive data. in rmii mode, this pin is reserved and can be left unconnected. hd43 d43 ethrxd3 reserved input/ output input/ output input input host data bus 43 bit 43 of the dsi data bus. system bus data 43 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data 3 in mii mode only, bit 3 of the ethernet receive data. in rmii mode, this pin is reserved and can be left unconnected. hd[44?45 ] d[44?56] reserved input/ output input/ output input host data bus 44?45 bits 44?45 of the dsi data bus. system bus data 44?45 for write transactions, the bus master drives valid data on this bus. for read transactions, the slave drives valid data on this bus. if the ethernet port is enabled and multiplexed with t he dsi/system bus, these pins are reserved and can be left unconnected. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
msc8122 technical data, rev. 13 1-6 freescale semiconductor signals/connections hd46 d46 ethtxd0 input/ output input/ output output host data bus 46 bit 46 of the dsi data bus. system bus data 46 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data 0 in mii and rmii modes, bit 0 of the ethernet transmit data. hd47 d47 ethtxd1 input/ output input/ output output host data bus 47 bit 47 of the dsi data bus. system bus data 47 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data 1 in mii and rmii modes, bit 1 of the ethernet transmit data. hd48 d48 ethtxd2 reserved input/ output input/ output output input host data bus 48 bit 48 of the dsi data bus. system bus data 48 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data 2 in mii mode only, bit 2 of the ethernet transmit data. in rmii mode, this pin is reserved and can be left unconnected. hd49 d49 ethtxd3 reserved input/ output input/ output output input host data bus 49 bit 49 of the dsi data bus. system bus data 49 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data 3 in mii mode only, bit 3 of the ethernet transmit data. in rmii mode, this pin is reserved and can be left unconnected. hd[50?53 ] d[50?53] reserved input/ output input/ output input host data bus 50?53 bits 50?53 of the dsi data bus. system bus data 50?53 for write transactions, the bus master drives valid data on this bus. for read transactions, the slave drives valid data on this bus. if the ethernet port is enabled and multiplexed with t he dsi/system bus, these pins are reserved and can be left unconnected. hd54 d54 ethtx_en input/ output input/ output output host data bus 54 bit 54 of the dsi data bus. system bus data 54 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data enable in mii and rmii modes, indicates that the transmit data is valid. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
direct slave interface, system bus, ethernet, and interrupt signals msc8122 technical data, rev. 13 freescale semiconductor 1-7 hd55 d55 ethtx_er reserved input/ output input/ output output input host data bus 55 bit 55 of the dsi data bus. system bus data 55 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet transmit data error in mii mode only, indicates a transmit data error. in rmii mode, this pin is reserved and can be left unconnected. hd56 d56 ethrx_dv ethcrs_dv input/ output input/ output input input host data bus 56 bit 56 of the dsi data bus. system bus data 56 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data valid indicates that the receive data is valid. ethernet carrier sense/receive data valid in rmii mode, indicates that a carrier is detected and after the connection is established that the receive data is valid. hd57 d57 ethrx_er input/ output input/ output input host data bus 57 bit 57 of the dsi data bus. system bus data 57 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet receive data error in mii and rmii modes, indicates a receive data error. hd58 d58 ethmdc input/ output input/ output output host data bus 58 bit 58 of the dsi data bus. system bus data 58 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet management clock in mii and rmii modes, used for the mdio reference clock. hd59 d59 ethmdio input/ output input/ output input/ output host data bus 59 bit 59 of the dsi data bus. system bus data 59 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet management data in mii and rmii modes, used for station management data input/output. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
msc8122 technical data, rev. 13 1-8 freescale semiconductor signals/connections hd60 d60 ethcol reserved input/ output input/ output input/ output input host data bus 60 bit 60 of the dsi data bus. system bus data 60 for write transactions, the bus master drives valid data on this line. for read trans actions, the slave drives valid data on this bus. ethernet collision in mii mode only, indicates that a collision was detected. in rmii mode, this pin is reserved and can be left unconnected. hd[61?63 ] d[61?63] reserved input/ output input/ output input host data bus 61?63 bits 61?63 of the dsi data bus. system bus data 61?63 for write transactions, the bus master drives valid data on this bus. for read transactions, the slave drives valid data on this bus. if the ethernet port is enabled and multiplexed with t he dsi/system bus, these pins are reserved and can be left unconnected. hcid[0?2] input host chip id 0?2 with hcid3, carries the chip id of the dsi. the dsi is accessed only if hcs is asserted and hcid[0?3] matches the chip_id, or if hbcs is asserted. hcid3 ha8 input input host chip id 3 with hci[0?2], carries the chip id of the dsi. the dsi is accessed only if hcs is asserted and hcid[0?3] matches the chip_id, or if hbcs is asserted. host bus address 8 used by an external host to acce ss the internal address space. ha[11?29] input host bus address 11?29 used by external host to acce ss the internal address space. hwbs[0?3] hdbs[0?3] hwbe[0?3] hdbe[0?3] input input input input host write byte strobes (in asynchronous dual mode) one bit per byte is used as a strobe for host write accesses. host data byte strobe (in asynchronous single mode) one bit per byte is used as a st robe for host read or write accesses host write byte enable (in synchronous dual mode) one bit per byte is used to indicate a va lid data byte for host read or write accesses. host data byte enable (in synchronous single mode) one bit per byte is used as a strobe enable for host write accesses table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
direct slave interface, system bus, ethernet, and interrupt signals msc8122 technical data, rev. 13 freescale semiconductor 1-9 hwbs[4?7] hdbs[4?7] hwbe[4?7] hdbe[4?7] pwe[4?7] psddqm[4?7] pbs[4?7] input input input input output output output host write byte strobes (in asynchronous dual mode) one bit per byte is used as a strobe for host write accesses. host data byte strobe (in asynchronous single mode) one bit per byte is used as a st robe for host read or write accesses host write byte enable (in synchronous dual mode) one bit per byte is used to indicate a valid data byte for host write accesses. host data byte enable (in synchronous single mode) one bit per byte is used as a str obe enable for host read or write accesses system bus write enable outputs of the bus general-purpose ch ip-select machine (gpcm). these pins select byte lanes for write operations. system bus sdram dqm from the sdram control machine. these pins se lect specific byte lanes of sdram devices. system bus upm byte select from the upm in the memory controller, these si gnals select specific byte lanes during memory operations. the timing of these pins is programmed in the upm. the actual driven value depends on the address and size of the transaction and the port size of the accessed device. hrds hrw hrde input input input host read data strobe (in asynchronous dual mode) used as a strobe for host read accesses. host read/write select (in asynchronous/synchronous single mode) host read/write select. host read data enable (in synchronous dual mode) indicates valid data for host read accesses. hbrst input host burst the host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode only. hdst[0?1] ha[9?10] input host data structure 0?1 defines the data structure of the host access in dsi little-endian mode. host bus address 9?10 used by an external host to acce ss the internal address space. hcs input host chip select dsi chip select. the dsi is accessed only if hcs is asserted and hcid[0?3] matches the chip_id. hbcs input host broadcast chip select dsi chip select for broadcast mode. enables more t han one dsi to share the same host chip-select pin for broadcast write accesses. hta output host transfer acknowledge upon a read access, indicates to the host when the data on the data bus is valid. upon a write access, indicates to the host that the data on the data bus was written to the dsi write buffer. hclkin input host clock input host clock signal for dsi synchronous mode. a[0?31] input/ output address bus when the msc8122 is in external master bus mode, these pins function as the system address bus. the msc8122 drives the address of its internal bus mast ers and responds to addresse s generated by external bus masters. when the msc8122 is in internal master bus mode, these pins ar e used as address lines connected to memory devices and are controlled by the msc8122 memory controller. tt0 ha7 input/ output bus transfer type 0 the bus master drives this pins during the addr ess tenure to specify the type of the transaction. host bus address 7 used by an external host to acce ss the internal address space. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
msc8122 technical data, rev. 13 1-10 freescale semiconductor signals/connections tt1 input/ output bus transfer type 1 the bus master drives this pins during the address tenure to specify the type of the transaction. some applications use only the tt1 signal, for example, from msc8122 to msc8122 or msc8122 to msc8101 and vice versa . in these applications, tt1 fu nctions as read/write signal. tt[2?4] cs[5?7] input/ output output bus transfer type 2?4 the bus master drives these pins during the address tenure to spec ify the type of the transaction. chip select 5?7 enables specific memory devices or peripherals connec ted to the system bus. cs[0?4] output chip select 0?4 enables specific memory devices or peripherals connec ted to the system bus. tsz[0?3] input/ output transfer size 0?3 the bus master drives these pins with a value indica ting the number of bytes transferred in the current transaction. tbst input/ output bus transfer burst the bus master asserts this pin to indicate that t he current transaction is a burst transaction (transfers eight words). irq1 gbl input output interrupt request 1 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. global 1 when a master within the msc8122 initiates a bus transact ion, it drives this pin. assertion of this pin indicates that the transfer is global and should be snooped by caches in the system. irq3 baddr31 input output interrupt request 3 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. burst address 31 1 five burst address output pins are outputs of the me mory controller. these pins connect directly to burstable memory devices without in ternal address incrementors cont rolled by the msc8122 memory controller. irq2 baddr30 input output interrupt request 2 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. burst address 30 1 five burst address output pins are outputs of the me mory controller. these pins connect directly to burstable memory devices without in ternal address incrementors cont rolled by the msc8122 memory controller. irq5 baddr29 input output interrupt request 5 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. bus burst address 29 1 five burst address output pins are outputs of the me mory controller. these pins connect directly to burstable memory devices without in ternal address incrementors cont rolled by the msc8122 memory controller. baddr28 output burst address 28 five burst address output pins are outputs of the me mory controller. these pins connect directly to burstable memory devices without in ternal address incrementors cont rolled by the msc8122 memory controller. baddr27 output burst address 27 five burst address output pins are outputs of the me mory controller. these pins connect directly to burstable memory devices without in ternal address incrementors cont rolled by the msc8122 memory controller. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
direct slave interface, system bus, ethernet, and interrupt signals msc8122 technical data, rev. 13 freescale semiconductor 1-11 br input/ output bus request 2 when an external arbiter is used, t he msc8122 asserts this pin as an output to request ownership of the bus. when the msc8122 controller is used as an internal arbiter, an external master asserts this pin as an input to request bus ownership. bg input/ output bus grant 2 when the msc8122 acts as an internal arbiter, it asse rts this pin as an output to grant bus ownership to an external bus master. when an external arbiter is us ed, it asserts this pin as an input to grant bus ownership to the msc8122. dbg input/ output data bus grant 2 when the msc8122 acts as an internal arbiter, it asse rts this pin as an output to grant data bus ownership to an external bus master. when an external arbiter is used, it asserts this pin as an input to grant data bus ownership to the msc8122. abb irq4 input/ output input address bus busy 1 the msc8122 asserts this pin as an output for t he duration of the address bus tenure. following an aack , which terminates the address bus tenure, the msc8122 deasserts abb for a fraction of a bus cycle and then stops driving this pin. the msc8122 does not assume bus ownership as long as it senses this pin is asserted as an inpu t by an external bus master. interrupt request 4 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. dbb irq5 input/ output input data bus busy 1 the msc8122 asserts this pin as an output for the duration of the data bus tenure. following a ta , which terminates the data bus tenure, the msc8122 deasserts dbb for a fraction of a bus cycle and then stops driving this pin. the msc8122 does not assume data bus ownership as long as it senses that this pin is asserted as an input by an external bus master. interrupt request 5 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ts input/ output bus transfer start assertion of this pin signals the beginning of a new address bus tenure. the msc8122 asserts this signal when one of its internal bus masters begins an address tenure. when the msc8122 senses that this pin is asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal msc8122 resources, memory controller support). aack input/ output address acknowledge a bus slave asserts this signal to indicate that it has identified the address tenure. assertion of this signal terminates the address tenure. artry input/ output address retry assertion of this signal indicates that the bus master should retry the bus transaction. an external master asserts this signal to enforce data coherency with its caches and to prevent deadlock situations. d[0?31] input/ output data bus bits 0?31 in write transactions, the bus master drives the valid data on this bus. in read transactions, the slave drives the valid data on this bus. reserved dp0 dreq1 ext_br2 input input/ output input input the primary configuration selection (default after reset) is reserved. system bus data parity 0 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and d[0?7]. dma request 1 used by an external peripher al to request dma service. external bus request 2 an external master asserts this pin to r equest bus ownership from the internal arbiter. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
msc8122 technical data, rev. 13 1-12 freescale semiconductor signals/connections irq1 dp1 dack1 ext_bg2 input input/ output output output interrupt request 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 1 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and d[8?15]. dma acknowledge 1 the dma controller drives this output to acknowledge the dma transaction on the bus. external bus grant 2 2 the msc8122 asserts this pin to grant bus ownership to an external bus master. irq2 dp2 dack2 ext_dbg2 input input/ output output output interrupt request 2 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 2 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and d[16?23]. dma acknowledge 2 the dma controller drives this output to acknowledge the dma transaction on the bus. external data bus grant 2 2 the msc8122 asserts this pin to grant data bus ownership to an external bus master. irq3 dp3 dreq2 ext_br3 input input/ output input input interrupt request 3 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 3 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and d[24?31]. dma request 2 used by an external peripher al to request dma service. external bus request 3 2 an external master should assert this pin to request bus ownership from the internal arbiter. irq4 dp4 dack3 ext_dbg3 input input/ output output output interrupt request 4 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 4 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and d[32?39]. dma acknowledge 3 the dma controller drives this output to acknowledge the dma transaction on the bus. external data bus grant 3 2 the msc8122 asserts this pin to grant data bus ownership to an external bus master. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
direct slave interface, system bus, ethernet, and interrupt signals msc8122 technical data, rev. 13 freescale semiconductor 1-13 irq5 dp5 dack4 ext_bg3 input input/ output output output interrupt request 5 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 5 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and d[40?47]. dma acknowledge 4 the dma controller drives this output to acknowledge the dma transaction on the bus. external bus grant 3 2 the msc8122 asserts this pin to grant bus ownership to an external bus. irq6 dp6 dreq3 input input/ output input interrupt request 6 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 6 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and d[48?55]. dma request 3 used by an external peripher al to request dma service. irq7 dp7 dreq4 input input/ output input interrupt request 7 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. system bus data parity 7 the agent that drives the data bus also drives t he data parity signals. the value driven on the data parity 7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and d[56?63]. dma request 4 used by an external peripher al to request dma service. ta input/ output transfer acknowledge indicates that a data beat is valid on the data bus. for single-beat transfers, ta assertion indicates the termination of the transfer. for burst transfers, ta is asserted eight times to indicate the transfer of eight data beats, with the last assertion indicating the termination of the burst transfer. tea input/ output transfer error acknowledge indicates a failure of the data tenure transaction.the masters within the msc8122 monitor the state of this pin. the msc8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not complete. nmi input non-maskable interrupt when an external device asserts this line, it generates an non-maskable interrupt in the msc8122, which is processed internally (defaul t) or is directed to an external host for processing (see nmi_out ). nmi_out output non-maskable interrupt output an open-drain pin driven from the msc8122 internal interrupt controller. assertion of this output indicates that a non-maskable interrupt is pending in the msc8122 internal interrupt controller, waiting to be handled by an external host. psdval input/ output port size data valid indicates that a data beat is valid on the data bus. the difference between the ta pin and the psdval pin is that the ta pin is asserted to indicate data transfer terminations, while the psdval signal is asserted with each data beat movement. when ta is asserted, psdval is always asserted. however, when psdval is asserted, ta is not necessarily asserted. for exampl e, if the dma controller initiates a double word (2 64 bits) transaction to a memory device with a 32-bit port size, psdval is asserted three times without ta and, finally, both pins are asserted to terminate the transfer. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
msc8122 technical data, rev. 13 1-14 freescale semiconductor signals/connections 1.5 memory co ntroller signals refer to the memory controller chapter in the msc8122 reference manual for details on configuring these signals. irq7 int_out input output interrupt request 7 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. interrupt output assertion of this output indicates that an unmasked interrupt is pending in the msc8122 internal interrupt controller. notes: 1. see the system interface unit (siu) chapter in the msc8122 reference manual for details on how to configure these pins. 2. when used as the bus control arbiter, the msc8122 can support up to three external bus masters. each master uses its own set of bus request, bus grant, and data bus grant signals ( br / bg / dbg , ext_br2 / ext_bg2 / ext_dbg2 , and ext_br3 / ext_bg3 / ext_dbg3 ). each of these signal sets must be configured to indicate whether the external master is or is not a msc8122 master device. see the bus configuration regi ster (bcr) description in the system interface unit (siu) chapter in the msc8122 reference manual for details on how to configure these pi ns. the second and third set of pins is defined by ext_xxx to indicate that they can only be used with external master devices. the first set of pins ( br / bg / dbg ) have a dual function. when the msc8122 is not the bus arbiter, it uses these signals ( br / bg / dbg ) to obtain master control of the bus. table 1-6. memory controller signals signal name type description bctl0 output system bus buffer control 0 controls buffers on the data bus. usually used with bctl1 . the exact function of this pin is defined by the value of siumcr[bctlc]. bctl1 cs5 output output system bus buffer control 1 controls buffers on the data bus. usually used with bctl0 . the exact function of this pin is defined by the value of siumcr[bctlc]. system and local bus chip select 5 enables specific memory devices or peripherals connected to msc8122 buses. bm[0?2] tc[0?2] bnksel[0?2] input input/ output output boot mode 0?2 defines the boot mode of the msc8122. this signal is sampled on poreset deassertion. transfer code 0?2 the bus master drives these pins during the addr ess tenure to specify the type of the code. bank select 0?2 selects the sdram bank when the msc8122 is in 60x-compatible bus mode. ale output address latch enable controls the external address latc h used in an external master bus. pwe[0?3] psddqm[0?3] pbs[0?3] output output output system bus write enable outputs of the bus general-purpose ch ip-select machine (gpcm). these pins select byte lanes for write operations. system bus sdram dqm from the sdram control machine. these pins se lect specific byte lanes of sdram devices. system bus upm byte select from the upm in the memory controller, these si gnals select specific byte lanes during memory operations. the timing of these pins is programmed in the upm. the actual driven value depends on the address and size of the transaction and the port size of the accessed device. table 1-5. dsi, system bus, ethernet, and interrupt signals (continued) signal name type description
memory controller signals msc8122 technical data, rev. 13 freescale semiconductor 1-15 psda10 pgpl0 output output system bus sdram a10 from the bus sdram controller. the precharge co mmand defines which bank is precharged. when the row address is driven, it is a part of the row address. when column address is driven, it is a part of column address. system bus upm general-purpose line 0 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. psdwe pgpl1 output output system bus sdram write enable from the bus sdram controller. should connect to sdram we input. system bus upm general-purpose line 1 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. poe psdras pgpl2 output output output system bus output enable from the bus gpcm. controls the output buffe r of memory devices during read operations. system bus sdram ras from the bus sdram controller. should connect to sdram ras input. system bus upm general-purpose line 2 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. psdcas pgpl3 output output system bus sdram cas from the bus sdram controller. should connect to sdram cas input. system bus upm general-purpose line 3 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. pgta pupmwait pgpl4 ppbs input input output output system gpcm ta terminates external transactions during gpcm operation. requires an external pull-up resistor for proper operation. system bus upm wait an external device holds this pin low to force the up m to wait until the device is ready to continue the operation. system bus upm general-purpose line 4 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. system bus parity byte select in systems that store data parity in a separate chip, this output is used as the byte-select for that chip. psdamux pgpl5 output output system bus sdram address multiplexer controls the system bus sdram address multiplexer when the msc8122 is in external master mode. system bus upm general-purpose line 5 one of six general-purpose output lines from the upm. the values and timing of this pin are programmed in the upm. table 1-6. memory controller signals (continued) signal name type description
msc8122 technical data, rev. 13 1-16 freescale semiconductor signals/connections 1.6 gpio, tdm, uart, and timer signals the general-purpose input/output (gpio), time-division multiplexed (tdm), universal asynchronous receiver/transmitter (uart), and timer signals are grouped together because they use a common set of signal lines. individual assignment of a signal to a specific signal line is configured through internal registers. table 1-7 describes the signals in this group. table 1-7. gpio, tdm, uart, ethernet, and timer signals signal name type description gpio0 chip_id0 irq4 ethtxd0 input/ output input input output general-purpose input output 0 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. chip id 0 determines the chip id of the msc8122 dsi. it is sampled on the rising edge of poreset signal. interrupt request 4 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet transmit data 0 for mii or rmii mode, bit 0 of the ethernet transmit data. gpio1 timer0 chip_id1 irq5 ethtxd1 input/ output input/ output input input output general-purpose input output 1 one of 32 gpio pins used as gpio or as one of tw o dedicated inputs or one of two dedicated outputs. timer 0 each signal is configured as either input to or output from the counter. see the msc8122 reference manual for configuration details. chip id 1 determines the chip id of the msc8122 dsi. it is sampled on the rising edge of poreset signal. interrupt request 5 one of the fifteen external lines that can request a servic e routine, via the internal interrupt controller, from the sc140 core. ethernet transmit data 1 for mii or rmii mode, bit 1 of the ethernet transmit data. gpio2 timer1 chip_id2 irq6 input/ output input/ output input input general-purpose input output 2 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual . timer 1 each signal is configured as either input to or out put from the counter. for the configuration of the pin direction, refer to the msc8122 reference manual . chip id 2 determines the chip id of the msc8122 dsi. it is sampled on the rising edge of poreset signal. interrupt request 6 one of the fifteen external lines that can request a servic e routine, via the internal interrupt controller, from the sc140 core.
gpio, tdm, uart, and timer signals msc8122 technical data, rev. 13 freescale semiconductor 1-17 gpio3 tdm3tsyn irq1 ethtxd2 input/ output input/ output input output general-purpose input output 3 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 transmit frame sync transmit frame sync for tdm 3. interrupt request 1 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet transmit data 2 for mii mode only, bit 2 of the ethernet transmit data. gpio4 tdm3tclk irq2 ethtx_er input/ output input input output general-purpose input output 4 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 transmit clock transmit clock for tdm 3 interrupt request 2 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet transmit data error for mii mode only, indicates whether a transmit data error occurred. gpio5 tdm3tdat irq3 ethrxd3 input/ output input/ output input input general-purpose input/output 5 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 serial transmitter data the serial transmit data signal for tdm 3. as an output, it provides the data_d signal for tdm 3. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 3 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data 3 for mii mode only, bit 3 of the ethernet receive data. gpio6 tdm3rsyn irq4 ethrxd2 input/ output input/ output input input general-purpose input output 6 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 receive frame sync the receive sync signal for tdm 3. as an input, this can be the data_b data signal for tdm 3.for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 4 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data 2 for mii mode only, bit 2 of the ethernet receive data. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
msc8122 technical data, rev. 13 1-18 freescale semiconductor signals/connections gpio7 tdm3rclk irq5 ethtxd3 input/ output input/ output input output general-purpose input output 7 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 receive clock the receive clock signal for tdm 3. as an output, this can be the data_c data signal for tdm 3. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 5 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet transmit data 3 for mii mode only, bit 3 of the ethernet transmit data. gpio8 tdm3rdat irq6 ethcol input/ output input/ output input input general-purpose input output 8 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm3 serial receiver data the receive data signal for tdm 3. as an input, this can be the data_a data signal for tdm 3. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 6 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet collision for mii mode only, indicates whether a collision was detected. gpio9 tdm2tsyn irq7 ethmdio input/ output input/ output input input/ output general-purpose input output 9 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm2 transmit frame sync transmit frame sync for tdm 2. interrupt request 7 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet management data station management data input/output line in mii, rmii, and smii modes. gpio10 tdm2tclk irq8 ethrx_dv ethcrs_dv nc input/ output input input input input input general-purpose input output 10 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm 2 transmit clock transmit clock for tdm 2. interrupt request 8 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data valid in mii mode, this signal indicates that the receive data is valid. ethernet carrier sense/receive data valid in rmii mode, this signal indicates that a carrier is sense or that the receive data is valid. not connected for smii mode, this signal must be left unconnected. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
gpio, tdm, uart, and timer signals msc8122 technical data, rev. 13 freescale semiconductor 1-19 gpio11 tdm2tdat irq9 ethrx_er ethtxd input/ output input/ output input input output general-purpose input output 11 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm2 serial transmitter data the transmit data signal for tdm 2. as an output, this can be the data_d data signal for tdm 2. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 9 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data error in mii and rmii modes, indicates a receive data error. ethernet transmit data in smii, used as the ethernet transmit data line. gpio12 tdm2rsyn irq10 ethrxd1 ethsync input/ output input/ output input input output general-purpose input output 12 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm2 receive frame sync the receive sync signal for tdm 2. as an input, this can be the data_b data signal for tdm 2. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 10 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data 1 bit 1 of the ethernet receive data (mii and rmii mode). ethernet sync signal in smii mode, this is the ethernet sync signal input. gpio13 tdm2rclk irq11 ethmdc input/ output input/ output input output general-purpose input output 13 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm2 receive clock the receive clock signal for tdm 2. as an input, this can be the data_c data signal for tdm 2. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 11 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet management clock used for the mdio reference clock for mii, rmii, and smii modes. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
msc8122 technical data, rev. 13 1-20 freescale semiconductor signals/connections gpio14 tdm2rdat irq12 ethrxd0 nc input/ output input/ output input input input input general-purpose input output 14 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm2 serial receiver data the receive data signal for tdm 2. as an input, this can be the data_a data signal for tdm 2. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 12 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. ethernet receive data 0 bit 0 of the ethernet receive data (mii and rmii). not connected for smii mode, this signal must be left unconnected. gpio15 tdm1tsyn dreq1 input/ output input/ output input general-purpose input output 15 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 transmit frame sync transmit frame sync for tdm 1. dma request 1 used by an external peripher al to request dma service. gpio16 tdm1tclk done1 drack1 input/ output input input/ output output general-purpose input output 16 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 transmit clock transmit clock for tdm 1. dma done 1 signifies that the channel must be terminated. if the dma controller generates done , the channel handling this peripheral is inactive. as an input to the dma controller, done closes the channel much like a normal channel closing. see the msc8122 reference manual chapters on dma controller and gpio for information on configuring the drack or done mode and pin direction. dma data request acknowledge 1 asserted by the dma controller to indicate that the dma controller has samp led the peripheral request. gpio17 tdm1tdat dack1 input/ output input/ output output general-purpose input output 17 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 serial transmitter data the transmit data signal for tdm 1. as an output, this can be the data_d data signal for tdm 1.for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. dma acknowledge 1 the dma controller drives this output to acknowledge the dma transaction on the bus. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
gpio, tdm, uart, and timer signals msc8122 technical data, rev. 13 freescale semiconductor 1-21 gpio18 tdm1rsyn dreq2 input/ output input/ output input general-purpose input output 18 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 receive frame sync the receive sync signal for tdm 1. as an input, this can be the data_b data signal for tdm 1. for configuration details, refer to the msc8122 reference manual . dma request 1 used by an external peripher al to request dma service. gpio19 tdm1rclk dack2 input/ output input/ output output general-purpose input output 19 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 receive clock the receive clock signal for tdm 1. as an input, this can be the data_c data signal for tdm 1. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. dma acknowledge 2 the dma controller drives this output to acknowledge the dma transaction on the bus. gpio20 tdm1rdat input/ output input/ output general-purpose input output 20 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm1 serial receiver data the receive data signal for tdm 1. as an input, this can be the data_a data signal for tdm 1. for configuration details, refer to the msc8122 reference manual . gpio21 tdm0tsyn input/ output input/ output general-purpose input output 21 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm0 transmit frame sync transmit frame sync for tdm 0. gpio22 tdm0tclk done2 drack2 input/ output input input/ output output general-purpose input output 22 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs.for details, refer to the msc8122 reference manual gpio programming model. tdm 0 transmit clock transmit clock for tdm 0. dma done 2 signifies that the channel must be terminated. if the dma generates done, the channel handling this peripheral is inactive. as an input to the dma, done closes the channel much like a normal channel closing. note: see the msc8122 reference manual chapters on dma and gpio for information on configuring the drack or done mode and pin direction. dma data request acknowledge 2 asserted by the dma controller to indicate that t he dma controller has sampl ed the peripheral request. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
msc8122 technical data, rev. 13 1-22 freescale semiconductor signals/connections gpio23 tdm0tdat irq13 input/ output input/ output input general-purpose input output 23 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm0 serial transmitter data the transmit data signal for tdm 0. as an output, this can be the data_d data signal for tdm 0. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 13 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. gpio24 tdm0rsyn irq14 input/ output input/ output input general-purpose input output 24 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm0 receive frame sync the receive sync signal for tdm 0. as an input, this can be the data_b data signal for tdm 0. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 14 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. gpio25 tdm0rclk irq15 input/ output input/ output input general-purpose input output 25 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm0 receive clock the receive clock signal for tdm 0. as an input, this can be the data_c data signal for tdm 0. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. interrupt request 15 one of fifteen external lines that can request a service routine, via the internal interrupt controller, from the sc140 core. gpio26 tdm0rdat input/ output input/ output general-purpose input output 26 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. tdm0 serial receiver data the receive data signal for tdm 0. as an input, this can be the data_a data signal for tdm 0. for configuration details, refer to the msc8122 reference manual chapter describing tdm operation. gpio27 dreq1 urxd input/ output input input general-purpose input output 27 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. dma request 1 used by an external peripher al to request dma service. uart receive data gpio28 dreq2 utxd input/ output input output general-purpose input output 28 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. dma request 2 used by an external peripher al to request dma service. uart transmit data table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
dedicated ethernet signals msc8122 technical data, rev. 13 freescale semiconductor 1-23 1.7 dedicated ethernet signals most ethernet signals are multiplexed with the dsi/system bus and the gpio ports. in addition to the multiplexed signals, there are three dedicated ethernet signals that are described in table 1-8. gpio29 chip_id3 ethtx_en input/ output input output general-purpose input output 29 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. chip id 3 determines the chip id of the msc8122 dsi. it is sampled on the rising edge of poreset signal. ethernet transmit enable used to enable the ethernet transmit controller for mii and rmii modes. gpio30 timer2 tmclk sda input/ output input/ output input input/ output general-purpose input output 30 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs.for details, refer to the msc8122 reference manual gpio programming model. timer 2 each signal is configured as either input to the counter or output from the counter . for the configuration of the pin direction, refer to the msc8122 reference manual . external timer clock an external timer can connect directly to the siu as the siu clock. i 2 c-bus data line this is the data line for the i 2 c bus. gpio31 timer3 scl input/ output input/ output input/ output general-purpose input output 31 one of 32 gpio pins used as gpio or as one of two dedicated inputs or one of two dedicated outputs. for details, refer to the msc8122 reference manual gpio programming model. timer 3 each signal is configured as either input to or out put from the counter. for the configuration of the pin direction, refer to the msc8122 reference manual . i 2 c-bus clock line this the clock line for the i 2 c bus. table 1-8. dedicated ethernet signals signal name type signal description ethrx_clk ethsync_in input input receive clock in mii mode, provides the timing reference for the receive signals. sync input in smii mode, is the sync signal input line. ethtx_clk ethref_clk ethclock input input input transmit clock in mii mode, provides the timing reference for transmit signals. reference clock in rmii mode, provides the timing reference. ethernet clock in smii mode, provides the ethernet clock signal. table 1-7. gpio, tdm, uart, ethernet, and timer signals (continued) signal name type description
msc8122 technical data, rev. 13 1-24 freescale semiconductor signals/connections 1.8 eonce event and jtag test access port signals the msc8122 uses two sets of debugging signals for the two types of internal debugging modules: eonce and the jtag tap controller. each internal sc140 core has an eonce module, but they are all accessed externally by the same two signals ee0 and ee1 . the msc8122 supports the standard set of test access port (tap) signals defined by ieee 1149.1 standard test access port and boundary-scan architecture specification and described in ta b le 1-9 . 1.9 reserved signals ethcrs ethrxd input input carrier sense in mii mode, indicates that either the transmit or receive medium is non-idle. ethernet receive data in smii mode, used for the ethernet receive data. table 1-9. jtag tap signals signal name type signal description ee0 input eonce event bit 0 puts the internal sc140 cores into debug mode. ee1 output eonce event bit 1 indicates that at least one on-device sc140 core is in debug mode. tck input test clock? synchronizes jtag test logic. tdi input test data input? a test data serial signal for test instructions and data. tdi is sampled on the rising edge of tck and has an internal pull-up resistor. tdo output test data output? a test data serial signal for test instructions and data. tdo can be tri-stated. the signal is actively driven in the shift-ir and shift-dr controller states and changes on the falling edge of tck. tms input test mode select? sequences the test controller state machine, is sampled on the rising edge of tck, and has an internal pull-up resistor. trst input test reset? asynchronously initializes the test controller; must be asserted during power up. table 1-10. reserved signals signal name type signal description test input test for manufacturing testing. you must connect this pin to gnd. table 1-8. dedicated ethernet signals signal name type signal description
msc8122 technical data, rev. 13 freescale semiconductor 2-1 specifications 2 this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications. for additional information, see the msc8122 user?s guide and msc8122 reference manual . 2.1 maximum ratings in calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a ?maximum? value for a specification never occurs in the same device with a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ).
msc8122 technical data, rev. 13 2-2 freescale semiconductor specifications ta b l e 2 -1 describes the maximum electrical ratings for the msc8122. 2.2 recommended operating conditions ta b l e 2 -2 lists recommended operating conditions. proper device operation outside of these conditions is not guaranteed. table 2-1. absolute maximum ratings rating symbol value unit core and pll supply voltage v dd ?0.2 to 1.6 v i/o supply voltage v ddh ?0.2 to 4.0 v input voltage v in ?0.2 to 4.0 v maximum operating temperature: ? standard range ? extended range t j 90 105 c c minimum operating temperature ? standard range ? extended range t j 0 ?40 c c storage temperature range t stg ?55 to +150 c notes: 1. functional operating conditions are given in table 2-2 . 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the listed limits may affect device reliability or cause permanent damage. 3. section 4.5 , thermal considerations includes a formula for computing the chip junction temperature (t j ). table 2-2. recommended operating conditions rating symbol value unit core and pll supply voltage: ? standard ? 400 mhz ? 500 mhz ? reduced (300 and 400 mhz) v dd v ccsyn 1.14 to 1.26 1.16 to 1.24 1.07 to 1.13 v v v i/o supply voltage v ddh 3.135 to 3.465 v input voltage v in ?0.2 to v ddh +0.2 v operating temperature range: ? standard ? extended t j t j 0 to 90 ?40 to 105 c c
thermal characteristics msc8122 technical data, rev. 13 freescale semiconductor 2-3 2.3 thermal characteristics ta b l e 2 -3 describes thermal characteristics of the msc8122 for the fc-pbga packages. section 4.5 , thermal considerations provides a detailed explanation of these characteristics. 2.4 dc electrical characteristics this section describes the dc electrical characteristics for the msc8122. the measurements in table 2-4 assume the following system conditions: ?t a = 25 c ? v dd = ? 300/400 mhz 1.1 v nominal = 1.07?1.13 v dc ? 400 mhz 1.2 v nominal = 1.14?1.26 v dc ? 500 mhz 1.2 v nominal = 1.16?1.24 v dc ? v ddh = 3.3 v 5% v dc ? gnd = 0 v dc note: the leakage current is measured for nominal v ddh and v dd . table 2-3. thermal characteristics for the msc8122 characteristic symbol fc-pbga 20 20 mm 5 unit natural convection 200 ft/min (1 m/s) airflow junction-to-ambient 1, 2 r ja 26 21 c/w junction-to-ambient, four-layer board 1, 3 r ja 19 15 c/w junction-to-board (bottom) 4 r jb 9 c/w junction-to-case 5 r jc 0.9 c/w junction-to-package-top 6 jt 1 c/w notes: 1. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power di ssipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 wit h the board horizontal. 4. thermal resistance between the die and the printed circuit boar d per jedec jesd 51-8. boar d temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per jedec jesd51-2.
msc8122 technical data, rev. 13 2-4 freescale semiconductor specifications 2.5 ac timings the following sections include illustrations and tables of clock diagrams, signals, and parallel i/o outputs and inputs. when systems such as dsp farms are developed using the dsi, use a device loading of 4 pf per pin. ac timings are based on a 20 pf load, except where noted otherwise, and a 50 transmission line. for loads smaller than 20 pf, subtract 0.06 ns per pf down to 10 pf load. for loads larger than 20 pf, add 0.06 ns for siu/ethernet/dsi delay and 0.07 ns for gpio/tdm/timer delay. when calculating overall loading, also consider additional rc delay. table 2-4. dc electrical characteristics characteristic symbol min typical max unit input high voltage 1 , all inputs except clkin v ih 2.0 ? 3.465 v input low voltage 1 v il gnd 0 0.4 v clkin input high voltage v ihc 2.4 3.0 3.465 v clkin input low voltage v ilc gnd 0 0.4 v input leakage current, v in = v ddh i in ?1.0 0.09 1 a tri-state (high impedance off state) leakage current, v in = v ddh i oz ?1.0 0.09 1 a signal low input current, v il = 0.4 v 2 i l ?1.0 0.09 1 a signal high input current, v ih = 2.0 v 2 i h ?1.0 0.09 1 a output high voltage, i oh = ?2 ma, except open drain pins v oh 2.0 3.0 ? v output low voltage, i ol = 3.2 ma v ol ? 0 0.4 v internal supply current: ? wait mode ? stop mode i ddw i dds ? ? 375 3 290 3 ? ? ma ma typical power 400 mhz at 1.2 v 4 p ? 1.15 ? w notes: 1. see figure 2-1 for undershoot and overshoot voltages. 2. not tested. guaranteed by design. 3. measured for 1.2 v core at 25c junction temperature. 4. the typical power values were measured using an efr code with the device running at a juncti on temperature of 25c. no peripherals were enabled and the icache was not enabled. the source code was optimized to use all the alus and agus and all four cores. it was created using codewarrior ? 2.5. these values are provided as ex amples only. power consumption is application dependent and varies widely. to assure proper board des ign with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your applic ation and use the design guidelines in chapter 4 of this document and in msc8102, msc8122, and msc8126 thermal management design guidelines (an2601). figure 2-1. overshoot/undershoot voltage for v ih and v il gnd gnd ? 0.3 v gnd ? 0.7 v v il v ih must not exceed 10% of clock period v ddh + 17% v ddh + 8% v ddh
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-5 2.5.1 output buffer impedances 2.5.2 start-up timing starting the device requires coordination among several input sequences including clocking, reset, and power. section 2.5.3 describes the clocking characteristics. section 2.5.4 describes the reset and power-up characteristics. you must use the following guidelines when starting up an msc8122 device: ? poreset and trst must be asserted externally for the duration of the power-up sequence. see table 2-10 for timing. ? if possible, bring up the v dd and v ddh levels together. for designs with separate power supplies, bring up the v dd levels and then the v ddh levels (see figure 2-3 ). ? clkin should start toggling at least 16 cycles (starting after v ddh reaches its nominal level) before poreset deassertion to guarantee correct device operation (see figure 2-2 and figure 2-3 ). ? clkin must not be pulled high during v ddh power-up. clkin can toggle during this period. the following figures show acceptable start-up sequence examples. figure 2-2 shows a sequence in which v dd and v ddh are raised together. figure 2-3 shows a sequence in which v ddh is raised after v dd and clkin begins to toggle as v ddh rises. table 2-5. output buffer impedances output buffers typical impedance ( ) system bus 50 memory controller 50 parallel i/o 50 note: these are typical values at 65c. the impedance may vary by 25% depending on device proce ss and operating temperature. figure 2-2. start-up sequence with v dd and v ddh raised together voltage time o.5 v 3.3 v 1.2 v v ddh nominal level poreset /trst asserted v dd nominal level clkin starts toggling v dd /v ddh applied poreset /trst deasserted 1 2.2 v v ddh = nominal value v dd = nominal value
msc8122 technical data, rev. 13 2-6 freescale semiconductor specifications 2.5.3 clock and timing signals the following sections include a description of clock signal characteristics. table 2-6 shows the maximum frequency values for internal (core, reference, bus, and dsi) and external ( clkin and clkout ) clocks. the user must ensure that maximum frequency values are not exceeded. figure 2-3. start-up sequence with v dd raised before v ddh with clkin started with v ddh table 2-6. maximum frequencies characteristic maximum in mhz core frequency 300/400/500 reference frequency (refclk) 100/133/166 internal bus frequency (blck) 100/133/166 dsi clock frequency (hclkin) ? core frequency = 300 mhz ? core frequency = 400/500 mhz hclkin (min{70 mhz, clkout}) hclkin (min{100 mhz, clkout}) external clock frequency (clkin or clkout) 100/133/166 table 2-7. clock frequencies characteristics symbol 300 mhz device 400 mhz device 500 mhz device min max min max min max clkin frequency f clkin 20 100 20 133.3 20 166.7 bclk frequency f bclk 40 100 40 133.3 40 166.7 reference clock (refclk) frequency f refclk 40 100 40 133.3 40 166.7 output clock (clkout) frequency f clkout 40 100 40 133.3 40 166.7 sc140 core clock frequency f core 200 300 200 400 200 500 note: the rise and fall time of external clocks should be 3 ns maximum table 2-8. system clock parameters characteristic min max unit phase jitter between bclk and clkin ? 0.3 ns clkin frequency 20 see table 2-7 mhz clkin slope ? 3 ns pll input clock (after predivider) 20 100 mhz voltage time o.5 v 3.3 v 1.2 v v ddh nominal poreset /trst asserted v dd nominal clkin starts toggling v dd applied poreset /trst deasserted 1 v ddh applied v ddh = nominal v dd = nominal
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-7 2.5.4 reset timing the msc8122 has several inputs to the reset logic: ? power-on reset ( poreset ) ? external hard reset ( hreset ) ? external soft reset ( sreset ) ? software watchdog reset ? bus monitor reset ? host reset command through jtag all msc8122 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. the reset status register indicates the most recent sources to cause a reset. ta b le 2 - 9 describes the reset sources. table 2-10 summarizes the reset actions that occur as a result of the different reset sources. pll output frequency (vco output) ? 300 mhz core ? 400 mhz core ? 500 mhz core 800 1200 1600 2000 mhz mhz mhz mhz clkout frequency jitter 1 ? 200 ps clkout phase jitter 1 with clkin phase jitter of 100 ps. ? 500 ps notes: 1. peak-to-peak. 2. not tested. guaranteed by design. table 2-9. reset sources name direction description power-on reset ( poreset ) input initiates the power-on reset flow that resets the msc8122 and configures various attributes of the msc8122. on poreset , the entire msc8122 device is reset. spll states is reset, hreset and sreset are driven, the sc140 extended cores are reset, and system configuration is sampled. the clock mode (modck bits), reset configuration mode, boot mode, chip id, and use of either a dsi 64 bits port or a system bus 64 bits port are configured only when poreset is asserted. external hard reset ( hreset ) input/ output initiates the hard reset flow that configures various attributes of the msc8122. while hreset is asserted, sreset is also asserted. hreset is an open-drain pin. upon hard reset, hreset and sreset are driven, the sc140 extended cores are reset, and system configuration is sampled. the most configurable features are reconfigured. t hese features are defined in the 32-bit hard reset configuration word described in hard reset configuration word section of the reset chapter in the msc8122 reference manual . external soft reset ( sreset ) input/ output initiates the soft reset flow. the msc8122 detects an external assertion of sreset only if it occurs while the msc8122 is not asserting reset. sreset is an open-drain pin. upon soft reset, sreset is driven, the sc140 extended cores are reset, and system configuration is maintained. software watchdog reset internal when the msc8122 watchdog count reaches zero, a software watchdog reset is signalled. the enabled software watchdog event then generates an internal hard reset sequence. bus monitor reset internal when the msc8122 bus monitor count reaches zero , a bus monitor hard reset is asserted. the enabled bus monitor event then generates an internal hard reset sequence. host reset command through the tap internal when a host reset command is written through the test access port (tap), the tap logic asserts the soft reset signal and an internal soft reset sequence is generated. table 2-8. system clock parameters characteristic min max unit
msc8122 technical data, rev. 13 2-8 freescale semiconductor specifications 2.5.4.1 power-on reset ( poreset ) pin asserting poreset initiates the power-on reset flow. poreset must be asserted externally for at least 16 clkin cycles after v dd and v ddh are both at their nominal levels. 2.5.4.2 reset configuration the msc8122 has two mechanisms for writing the reset configuration: ? through the direct slave interface (dsi) ? through the system bus. when the reset configuration is written through the system bus, the msc8122 acts as a configuration master or a configuration slave. if configuration slave is selected, but no special configuration word is written, a default configuration word is applied. fourteen signal levels (see chapter 1 for signal description details) are sampled on poreset deassertion to define the reset configuration mode and boot and operating conditions: ? rstconf ? cnfgs ? dsisync ? dsi64 ? chip_id[0?3] ? bm[0?2] ? swte ? modck[1?2] table 2-10. reset actions for each reset source reset action/reset source power-on reset ( poreset ) hard reset ( hreset ) soft reset ( sreset ) external only external or internal (software watchdog or bus monitor) external jtag command: extest, clamp, or highz configuration pins sampled (refer to section 2.5.4.1 for details) . yes no no no spll state reset yes no no no system reset configuration write through the dsi yes no no no system reset configuration write though the system bus yes yes no no hreset driven yes yes no no siu registers reset yes yes no no ipbus modules reset (tdm, uart, timers, dsi, ipbus master, gic, hs, and gpio) yes yes yes yes sreset driven yes yes yes depends on command sc140 extended cores reset yes yes yes yes mqbs reset yes yes yes yes
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-9 2.5.4.3 reset timing tables ta b l e 2 -11 and figure 2-4 describe the reset timing for a reset configuration write through the direct slave interface (dsi) or through the system bus. table 2-11. timing for a reset configuration write through the dsi or system bus no. characteristics expression min max unit 1 required external poreset duration minimum ? clkin = 20 mhz ? clkin = 100 mhz (300 mhz core) ? clkin = 133 mhz (400 mhz core) ? clkin = 166 mhz (500 mhz core) 16/clkin 800 160 120 96 ? ? ? ? ns ns ns ns 2 delay from deassertion of external poreset to deassertion of internal poreset ? clkin = 20 mhz to 166 mhz 1024/clkin 6.17 51.2 s 3 delay from de-assertion of internal poreset to spll lock ? clkin = 20 mhz (rdf = 1) ? clkin = 100 mhz (rdf = 1) (300 mhz core) ? clkin = 133 mhz (rdf = 2) (400 mhz core) ? clkin = 166 mhz (rdf = 2) (500 mhz core) 6400/(clkin/rdf) (pll reference clock- division factor) 320 64 96 77 320 64 96 77 s s s s 5 delay from spll to hreset deassertion ? refclk = 40 mhz to 166 mhz 512/refclk 3.08 12.8 s 6 delay from spll lock to sreset deassertion ? refclk = 40 mhz to 166 mhz 515/refclk 3.10 12.88 s 7 setup time from assertion of rstconf , cnfgs, dsisync, dsi64, chip_id[0?3], bm[0?2], swte, and modck[1?2] before deassertion of poreset 3 ? ns 8 hold time from deassertion of poreset to deassertion of rstconf , cnfgs, dsisync, dsi64, chip_id[0?3], bm[0?2], swte, and modck[1?2] 5 ? ns note: timings are not tested, but are guaranteed by design. figure 2-4. timing diagram for a reset configuration write poreset internal hreset input output (i/o) sreset output (i/o) rstconf , cnfgs, dsisync, dsi64 chip_id[0?3], bm[0?2], swte, modck[1?2] host programs word spll is locked (no external indication) poreset reset configuration pins are sampled 1 2 modck[3?5] 1 + 2 3 5 6 spll locking period reset configuration write sequence during this period.
msc8122 technical data, rev. 13 2-10 freescale semiconductor specifications 2.5.5 system bus access timing 2.5.5.1 core data transfers generally, all msc8122 bus and system output signals are driven from the rising edge of the reference clock (refclk). the refclk is the clkin signal. memory controller signals, however, trigger on four points within a refclk cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge of refclk (and t3 at the falling edge), but the spacing of t2 and t4 depends on the pll clock ratio selected, as table 2-12 shows. figure 2-5 is a graphical representation of table 2-12 . table 2-12. tick spacing for memory controller signals bclk/sc140 clock tick spacing (t1 occurs at the rising edge of refclk) t2 t3 t4 1:4, 1:6, 1:8, 1:10 1/4 refclk 1/2 refclk 3/4 refclk 1:3 1/6 refclk 1/2 refclk 4/6 refclk 1:5 2/10 refclk 1/2 refclk 7/10 refclk figure 2-5. internal tick spacing for memory controller signals refclk t1 t2 t3 t4 refclk t1 t2 t3 t4 for 1:3 for 1:5 refclk t1 t2 t3 t4 for 1:4, 1:6, 1:8, 1:10
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-11 the upm machine and gpcm machine outputs change on the internal tick selected by the memory controller configuration. the ac timing specifications are relative to the internal tick. sdram machine outputs change only on the refclk rising edge. table 2-13. ac timing for siu inputs no. characteristic value for bus speed in mhz units ref = clkin ref = clkout 1.1 v 1.2 v 1.2 v 1.2 v 100/ 133 133 166 133 10 hold time for all signals after the 50% level of the refclk rising edge 0.5 0.5 0.5 0.5 ns 11a artry / abb set-up time before the 50% level of the refclk rising edge 3.1 3.0 3.0 3.0 ns 11b dbg / dbb / bg / br / tc set-up time before the 50% level of the refclk rising edge 3.6 3.3 3.3 3.3 ns 11c aack set-up time before the 50% level of the refclk rising edge 3.0 2.9 2.9 2.9 ns 11d ta / tea / psdval set-up time before the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 3.5 4.4 3.4 4.0 3.4 4.0 3.4 4.0 ns ns 12 data bus set-up time before refclk rising edge in normal mode ? data-pipeline mode ? non-pipeline mode 1.9 4.2 1.8 4.0 1.7 4.0 1.8 4.0 ns ns 13 1 data bus set-up time before the 50% level of the refclk rising edge in ecc and parity modes ? data-pipeline mode ? non-pipeline mode 2.0 8.2 2.0 7.3 2.0 7.3 2.0 7.3 ns ns 14 1 dp set-up time before the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 2.0 7.9 2.0 6.1 2.0 6.1 2.0 6.1 ns ns 15a ts and address bus set-up time before the 50% level of the refclk rising edge ? extra cycle mode (siubcr[exdd] = 0) ? no extra cycle mode (siubcr[exdd] = 1) 4.2 5.5 3.8 5.0 3.8 5.0 3.8 5.0 ns ns 15b address attributes: tt/ tbst /tsz/ gbl set-up time before the 50% level of the refclk rising edge ? extra cycle mode (siubcr[exdd] = 0) ? no extra cycle mode (siubcr[exdd] = 1) 3.7 4.8 3.5 4.4 3.5 4.4 3.5 4.4 ns ns 16 pupmwait signal set-up time before the 50% level of the refclk rising edge 3.7 3.7 3.7 3.7 ns 17 irqx setup time before the 50% level; of the refclk rising edge 3 4.0 4.0 4.0 4.0 ns 18 irqx minimum pulse width 3 6.0 + t refclk 6.0 + t refclk 6.0 + t refclk 6.0 + t refclk ns notes: 1. timings specifications 13 and 14 in non-pipeline mode are more restrictive than msc8102 timings. 2. values are measured from the 50% ttl transition level relative to the 50% level of the refclk rising edge. 3. guaranteed by design.
msc8122 technical data, rev. 13 2-12 freescale semiconductor specifications table 2-14. ac timing for siu outputs no. characteristic value for bus speed in mhz 3 units ref = clkin ref = clkout 1.1 v 1.2 v 1.2 v 1.2 v 100/ 133 133 166 100/133 30 2 minimum delay from the 50% level of the refclk for all signals 0.9 0.8 0.8 1.0 ns 31 psdval / tea / ta max delay from the 50% level of the refclk rising edge 6.0 4.9 4.9 5.8 ns 32a address bus max delay from the 50% level of the refclk rising edge ? multi-master mode (siubcr[ebm] = 1) ? single-master mode (siubcr[ebm] = 0) 6.4 5.3 5.5 4.2 5.5 3.9 6.4 5.1 ns ns 32b address attributes: tt[0?1]/ tbst /tsz/ gbl max delay from the 50% level of the refclk rising edge 6.4 5.1 5.1 6.0 ns 32c address attributes: tt[2?4]/tc max delay from the 50% level of the refclk rising edge 6.9 5.7 5.7 6.6 ns 32d baddr max delay from the 50% level of the refclk rising edge 5.2 4.2 4.2 5.1 ns 33a data bus max delay from the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 4.8 7.1 3.9 6.1 3.7 6.1 4.8 7.0 ns ns 33b dp max delay from the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 6.0 7.5 5.3 6.5 5.3 6.5 6.2 7.4 ns ns 34 memory controller signals/ale/ cs[0?4] max delay from the 50% level of the refclk rising edge 5.1 4.2 3.9 5.1 ns 35a dbg / bg / br / dbb max delay from the 50% level of the refclk rising edge 6.0 4.7 4.7 5.6 ns 35b aack / abb / ts / cs[5?7] max delay from the 50% level of the refclk rising edge 5.5 4.5 4.5 5.4 ns notes: 1. values are measured from the 50% level of the refclk risi ng edge to the 50% signal level and assume a 20 pf load except where otherwise specified. 2. the load for specification 30 is 10 pf. the load for the other spec ifications in this table is 20 pf. for a 15 pf load, subtrac t 0.3 ns from the listed value. 3. the maximum bus frequency depends on the mode: ? in 60x-compatible mode connected to another msc8122 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pf output capacitance. you must also account for other influences that can affect timing, such as on- board clock skews, on-board noise delays, and so on. ? in single-master mode, the frequency depends on t he timing of the devices connected to the msc8122. ? to achieve maximum performance on the bus in single-master mode, disable the dbb signal by writing a 1 to the siumcr[bdd] bit. see the siu chapter in the msc8122 reference manual for details.
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-13 refclk aack /artry /ta /tea /dbg /bg /br data bus inputs?normal mode pupmwait input psdva l/tea /ta outputs address bus/tt[0?4]/tc[0?2]/tbst /tsz[0?3]/gbl outputs data bus outputs min delay for all output pins 11 10 10 10 12 15 31 32a/b 33a 30 dp outputs 33b memory controller/ale outputs 34 data bus inputs?ecc and parity modes 10 13 aack /abb /ts /dbg /bg /br /dbb /cs outputs 35 baddr outputs 32c dp inputs 14 address bus/ts /tt[0?4]/tc[0?2]/ 16 psdval /abb /dbb inputs tbst /tsz[0?3]/gbl inputs 18 17 irqx inputs
msc8122 technical data, rev. 13 2-14 freescale semiconductor specifications 2.5.5.2 clkin to clkout skew table 2-16 describes the clkout- to- clkin skew timing . for designs that use the clkout synchronization mode, use the skew values listed in table 2-15 to adjust the rise- to-fall timing values specified for clkin synchronization. figure 2-6 shows the relationship between the clkout and clkin timings. table 2-15. clkout skew no. characteristic min 1 max 1 units 20 rise-to-rise skew ?v dd = 1.1 v ?v dd = 1.2 v 0.0 0.0 0.95 0.85 ns ns 21 fall-to-fall skew ?v dd = 1.1 v ?v dd = 1.2 v ?1.5 ?0.8 1.0 1.0 ns ns 22 clkout phase (1.2 v, 133 mhz) ? phase high ? phase low 2.8 2.8 ? ? ns ns 23 clkout phase (1.1 v, 133 mhz) ? phase high ? phase low 2.2 2.2 ? ? ns ns 24 clkout phase (1.1 v, 100 mhz) ? phase high ? phase low 3.3 3.3 ? ? ns ns notes: 1. a positive number indicates that clkout precedes clkin, a negative number indicates that clkout follows clkin. 2. skews are measured in clock mode 29, with a clkin:clkout ratio of 1:1. the same skew is valid for all clock modes. 3. clkout skews are measured using a load of 10 pf. 4. clkout skews and phase are not measured for 500/166 mh z parts because these parts only use clkin mode. figure 2-6. clkout and clkin signals. clkin clkout 20 21
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-15 2.5.5.3 dma data transfers table 2-16 describes the dma signal timing . the dreq signal is synchronized with refclk . to achieve fast response, a synchronized peripheral should assert dreq according to the timings in table 2-16 . figure 2-7 shows synchronous peripheral interaction. table 2-16. dma signals no. characteristic ref = clkin ref = clkout (1.2 v only) units min max min max 37 dreq set-up time before the 50% level of the falling edge of refclk 5.0 ? 5.0 ? ns 38 dreq hold time after the 50% level of the falling edge of refclk 0.5 ? 0.5 ? ns 39 done set-up time before the 50% level of the rising edge of refclk 5.0 ? 5.0 ? ns 40 done hold time after the 50% level of the rising edge of refclk 0.5 ? 0.5 ? ns 41 dack / drack / done delay after the 50% level of the refclk rising edge 0.5 7.5 0.5 8.4 ns figure 2-7. dma signals refclk dreq done dack /done /drack 37 38 40 39 41
msc8122 technical data, rev. 13 2-16 freescale semiconductor specifications 2.5.6 dsi timing the timings in the following sections are based on a 20 pf capacitive load. 2.5.6.1 dsi asynchronous mode table 2-17. dsi asynchronous mode timing no. characteristics min max unit 100 attributes 1 set-up time before strobe ( hwbs[n] ) assertion 1.5 ? ns 101 attributes 1 hold time after data strobe deassertion 1.3 ? ns 102 read/write data strobe deassertion width: ? dcr[htaad] = 1 ? consecutive access to the same dsi ? different device with dcr[htadt] = 01 ? different device with dcr[htadt] = 10 ? different device with dcr[htadt] = 11 ? dcr[htaad] = 0 1.8 + t refclk 5 + t refclk 5 + (1.5 t refclk ) 5 + (2.5 t refclk ) 1.8 + t refclk ? ns ns ns ns ns 103 read data strobe deassertion to output data high impedance ? 8.5 ns 104 read data strobe assertion to output data active from high impedance 2.0 ? ns 105 output data hold time after read data strobe deassertion 2.2 ? ns 106 read/write data strobe assertion to hta active from high impedance 2.2 ? ns 107 output data valid to hta assertion 3.2 ? ns 108 read/write data strobe assertion to hta valid 2 ?1.1 v core ?1.2 v core ? ? 7.4 6.7 ns ns 109 read/write data strobe deassertion to output hta high impedance. (dcr[htaad] = 0, hta at end of access released at logic 0) ? 6.5 ns 110 read/write data strobe deassertion to output hta deassertion. (dcr[htaad] = 1, hta at end of access released at logic 1) ? 6.5 ns 111 read/write data strobe deassertion to output hta high impedance. (dcr[htaad] = 1, hta at end of access released at logic 1 ? dcr[htadt] = 01 ? dcr[htadt] = 10 ? dcr[htadt] = 11 ? 5 + t refclk 5 + (1.5 t refclk ) 5 + (2.5 t refclk ) ns ns ns 112 read/write data strobe assertion width 1.8 + t refclk ? ns 201 host data input set-up time before write data strobe deassertion 1.0 ? ns 202 host data input hold time after write data strobe deassertion ?1.1 v core ?1.2 v core 1.7 1.5 ? ? ns ns notes: 1. attributes refers to the following signals: hcs , ha[11?29], hcid[0?4], hdst, hrw, hrds , and hwbsn . 2. this specification is tested in dual-strobe mode. timing in single -strobe mode is guaranteed by design. 3. all values listed in this tabl e are tested or guaranteed by design.
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-17 figure 2-8 shows dsi asynchronous read signals timing. figure 2-8. asynchronous single- and dual-strobe modes read timing diagram hdbsn 1 ha[11?29] hcs hd[0?63] 102 100 105 101 103 104 109 108 106 hta 4 hcid[0?4] hdst hta 3 107 110 111 112 hrw 1 hwbsn 2 hrds 2 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. 3. hta released at logic 0 (dcr[htaad] = 0) at end of access; used with pull- down implementation. 4. hta released at logic 1 (dcr[htaad] = 1) at end of access; used with pull-up implementation.
msc8122 technical data, rev. 13 2-18 freescale semiconductor specifications figure 2-9 shows dsi asynchronous write signals timing. figure 2-10 shows dsi asynchronous broadcast write signals timing. figure 2-9. asynchronous single- and dual-strobe modes write timing diagram figure 2-10. asynchronous broadcast write timing diagram hd[0?63] 100 101 102 201 202 109 106 hwbsn 2 108 110 111 112 hdbsn 1 hta 4 hta 3 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. 3. hta released at logic 0 (dcr[htaad] = 0) at end of access; used with pull-down implementation. 4. hta released at logic 1 (dcr[htaad] = 1) at end of access; used with pull-up implementation. ha[11?29] hcs hcid[0?4] hdst hrw 1 hrds 2 hd[0?63] 100 101 102 201 202 hwbsn 2 112 hdbsn 1 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. ha[11?29] hcs hcid[0?4] hdst hrw 1 hrds 2
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-19 2.5.6.2 dsi synchronous mode table 2-18. dsi inputs in synchronous mode no. characteristic expression 1.1 v core 1.2 v core units min max min max 120 hclkin cycle time 1,2 htc 10.0 55.6 10.0 55.6 ns 121 hclkin high pulse width (0.5 0.1) htc 4.0 33.3 4.0 33.3 ns 122 hclkin low pulse width (0.5 0.1) htc 4.0 33.3 4.0 33.3 ns 123 ha[11?29] inputs set-up time ? 1.2 ? 1.2 ? ns 124 hd[0?63] inputs set-up time ? 0.6 ? 0.4 ? ns 125 hcid[0?4] inputs set-up time ? 1.3 ? 1.3 ? ns 126 all other inputs set-up time ? 1.2 ? 1.2 ? ns 127 all inputs hold time ? 1.5 ? 1.5 ? ns notes: 1. values are based on a frequency range of 18?100 mhz. 2. refer to table 2-6 for hclkin frequency limits. table 2-19. dsi outputs in synchronous mode no. characteristic 1.1 v core 1.2 v core units min max min max 128 hclkin high to hd[0?63] output active 2.0 ? 2.0 ? ns 129 hclkin high to hd[0?63] output valid ? 7.6 ? 6.3 ns 130 hd[0?63] output hold time 1.7 ? 1.7 ? ns 131 hclkin high to hd[0?63] output high impedance ? 8.3 ? 7.6 ns 132 hclkin high to hta output active 2.2 ? 2.0 ? ns 133 hclkin high to hta output valid ? 7.4 ? 5.9 ns 134 hta output hold time 1.7 ? 1.7 ? ns 135 hclkin high to hta high impedance ? 7.5 ? 6.3 ns figure 2-11. dsi synchronous mode signals timing diagram hclkin ha[11?29] input signals all other input signals hd[0?63] output signals hta output signal ~ ~ hd[0?63] input signals 120 127 123 126 127 122 121 131 130 129 128 133 135 134 132 ~ ~ ~ ~ hcid[0?4] input signals 125 127 127 124
msc8122 technical data, rev. 13 2-20 freescale semiconductor specifications 2.5.7 tdm timing table 2-20. tdm timing no. characteristic expression 1.1 v core 1.2 v core units min max min max 300 tdmxrclk/tdmxtclk tc 1 16 ? 16 ? ns 301 tdmxrclk/tdmxtclk high pulse width (0.5 0.1) tc 7 ? 7 ? ns 302 tdmxrclk/tdmxtclk low pulse width (0.5 0.1) tc 7 ? 7 ? ns 303 tdm receive all input set-up time 1.3 ? 1.3 ? ns 304 tdm receive all input hold time 1.0 ? 1.0 ? ns 305 tdmxtclk high to tdmxtdat/tdmxrclk output active 2,3 2.8 ? 2.8 ? ns 306 tdmxtclk high to tdmxtdat/tdmxrclk output ? 10.0 ? 8.8 ns 307 all output hold time 4 2.5 ? 2.5 ? ns 308 tdmxtclk high to tdmxtdat/tdmxrclk output high impedance 2,3 ? 10.7 ? 10.5 ns 309 tdmxtclk high to tdmxtsyn output valid 2 ? 9.7 ? 8.5 ns 310 tdmxtsyn output hold time 4 2.5 ? 2.5 ? ns notes: 1. values are based on a a maximum frequency of 62.5 mhz. the tdm interface supports any frequency below 62.5 mhz. devices operating at 300 mhz are limited to a maximum tdmxrclk/tdmxtclk frequency of 50 mhz. 2. values are based on 20 pf capacitive load. 3. when configured as an output, tdmxrclk acts as a second data link. see the msc8122 reference manual for details. 4. values are based on 10 pf capacitive load. figure 2-12. tdm inputs signals figure 2-13. tdm output signals tdmxrclk tdmxrdat tdmxrsyn 300 301 302 303 303 304 304 tdmxtclk tdmxtdat ~ ~ tdmxtsyn ~ ~ 305 306 308 307 300 301 302 310 309 tdmxrclk
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-21 2.5.8 uart timing table 2-21. uart timing no. characteristics expression min max un it 400 urxd and utxd inputs high/low duration 16 t refclk 160.0 ? ns 401 urxd and utxd inputs rise/fall time 10 ns 402 utxd output rise/fall time 10 ns figure 2-14. uart input timing figure 2-15. uart output timing utxd, urxd 400 inputs 400 401 401 utxd output 402 402
msc8122 technical data, rev. 13 2-22 freescale semiconductor specifications 2.5.9 timer timing 2.5.10 ethernet timing 2.5.10.1 management interface timing table 2-22. timer timing no. characteristics ref = clkin unit min max 500 timerx frequency 10.0 ? ns 501 timerx input high period 4.0 ? ns 502 timerx output low period 4.0 ? ns 503 timerx propagations delay from its clock input ?1.1 v core ?1.2 v core 3.1 2.8 9.5 8.1 ns ns figure 2-16. timer timing table 2-23. ethernet controller management interface timing no. characteristics min max unit 801 ethmdio to ethmdc rising edge set-up time 10 ? ns 802 ethmdc rising edge to ethmdio hold time 10 ? ns figure 2-17. mdio timing relationship to mdc 500 502 501 timerx (input) timerx (output) 503 valid ethmdc ethmdio 802 801
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-23 2.5.10.2 mii mode timing 2.5.10.3 rmii mode table 2-24. mii mode signal timing no. characteristics min max unit 803 ethrx_dv, ethrxd[0?3], ethrx_er to ethrx_clk rising edge set-up time 3.5 ? ns 804 ethrx_clk rising edge to ethrx_dv, ethrxd[0?3], ethrx_er hold time 3.5 ? ns 805 ethtx_clk to ethtx_en, ethtxd[0?3], ethtx_er output delay ?1.1 v core ?1.2 v core 1 1 14.6 12.6 ns ns figure 2-18. mii mode signal timing table 2-25. rmii mode signal timing no. characteristics 1.1 v core 1.2 v core unit min max min max 806 ethtx_en,ethrxd[0?1], ethcrs_dv, ethrx_er to ethref_clk rising edge set-up time 1.6 ? 2 ? ns 807 ethref_clk rising edge to ethrxd[0?1], ethcrs_dv, ethrx_er hold time 1.6 ? 1.6 ? ns 811 ethref_clk rising edge to ethtxd[0?1], ethtx_en output delay. 3 12.5 3 11 ns figure 2-19. rmii mode signal timing valid ethrx_clk ethrx_dv ethrxd[0?3] ethtx_clk ethrx_er ethtx_en ethtxd[0?3] valid valid ethtx_er 803 804 805 valid ethref_clk ethcrs_dv ethrxd[0?1] ethrx_er 807 806 ethtx_en ethtxd[0?1] valid valid 811
msc8122 technical data, rev. 13 2-24 freescale semiconductor specifications 2.5.10.4 smii mode 2.5.11 gpio timing table 2-26. smii mode signal timing no. characteristics min max unit 808 ethsync_in, ethrxd to ethclock rising edge set-up time 1.0 ? ns 809 ethclock rising edge to ethsync_in, ethrxd hold time 1.0 ? ns 810 ethclock rising edge to ethsync, ethtxd output delay ? 1.1 v core. ? 1.2 v core. 1.5 1 1.5 1 6.0 2 5.0 2 ns ns notes: 1. measured using a 5 pf load. 2. measured using a 15 pf load. figure 2-20. smii mode signal timing table 2-27. gpio timing no. characteristics ref = clkin ref = clkout (1.2 v only) unit min max min max 601 refclk edge to gpio out valid (gpio out delay time) ? 6.1 ? 6.9 ns 602 refclk edge to gpio out not valid (gpio out hold time) 1.1 ? 1.3 ? ns 603 refclk edge to high impedance on gpio out ? 5.4 ? 6.2 ns 604 gpio in valid to refclk edge (gpio in set-up time) 3.5 ? 3.7 ? ns 605 refclk edge to gpio in not valid (gpio in hold time) 0.5 ? 0.5 ? ns valid ethclock ethsync_in ethrxd ethsync ethtxd valid valid 810 809 808
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-25 2.5.12 ee signals figure 2-22 shows the signal behavior of the ee pins. 2.5.13 jtag signals figure 2-21. gpio timing table 2-28. ee pin timing number characteristics type min 65 ee0 (input) asynchronous 4 core clock periods 66 ee1 (output) synchronous to core clock 1 core clock period notes: 1. the core clock is the sc140 core clock. the ratio between t he core clock and clkout is configured during power-on-reset. 2. refer to table 1-4 on page 1-6 for details on ee pin functionality. figure 2-22. ee pin timing table 2-29. jtag timing no. characteristics all frequencies unit min max 700 tck frequency of operation (1/(t c 4); maximum 25 mhz) 0.0 25 mhz 701 tck cycle time 40.0 ? ns 702 tck clock pulse width measured at v m = 1.6 v ?high ?low 20.0 16.0 ? ? ns ns 703 tck rise and fall times 0.0 3.0 ns refclk gpio (output) gpio (input) valid 603 high impedance 604 605 602 60 1 ee1 out ee0 in 65 66
msc8122 technical data, rev. 13 2-26 freescale semiconductor specifications 704 boundary scan input data set-up time 5.0 ? ns 705 boundary scan input data hold time 20.0 ? ns 706 tck low to output data valid 0.0 30.0 ns 707 tck low to output high impedance 0.0 30.0 ns 708 tms, tdi data set-up time 5.0 ? ns 709 tms, tdi data hold time 20.0 ? ns 710 tck low to tdo data valid 0.0 20.0 ns 711 tck low to tdo high impedance 0.0 20.0 ns 712 trst assert time 100.0 ? ns 713 trst set-up time to tck low 30.0 ? ns note: all timings apply to once module data transfers as well as any other transfers via the jtag port. figure 2-23. test clock input timing diagram figure 2-24. boundary scan (jtag) timing diagram table 2-29. jtag timing (continued) no. characteristics all frequencies unit min max tck (input) v m v m v ih v il 701 702 703 703 tck (input) data inputs data outputs data outputs v ih v il input data valid output data valid 705 704 706 707
ac timings msc8122 technical data, rev. 13 freescale semiconductor 2-27 figure 2-25. test access port timing diagram figure 2-26. trst timing diagram tck (input) tdi (input) tdo (output) tdo (output) v ih v il input data valid output data valid tms 708 709 710 711 tck (input) trst (input) 713 712
msc8122 technical data, rev. 13 2-28 freescale semiconductor specifications
msc8122 technical data, rev. 13 freescale semiconductor 3-1 packaging 3 this section provides information on the msc8122 package, including diagrams of the package pinouts and tables showing how the signals discussed in chapter 1 are allocated. the msc8122 is available in a 431-pin flip chip- plastic ball grid array (fc-pbga). 3.1 package description figure 3-1 and figure 3-2 show top and bottom views of the package, including pinouts. to conform to jedec requirements, the package is based on a 23 23 position (20 20 mm) layout with the outside perimeter depopulated. therefore, ball position numbering starts with b2. signal names shown in the figures are typically the signal assigned after reset. signals that are only used during power-on reset ( swte , dsisync , dsi64 , modck[1?2] , cnfgs , and chip_id[0?3] ) are not shown in these figures if there is another signal assigned to the pin after reset. also, there are several signals that are designated as irq lines immediately after reset, but represent duplicate irq lines that should be reconfigured by the user. to represent these signals uniquely in the figures, the second functions ( baddr[29?31] , dp[1?7] , and int_out ) are used. ta b l e 3 -1 lists the msc8122 signals alphabetically by signal name. connections with multiple names are listed individually by each name. signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, name / name ). ta b l e 3 -2 lists the signals numerically by pin number. each pin number is listed once with the various signals that are multiplexed to it. for simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). note: for ethernet signals multiplexed with the dsi/system bus (mii and rmii modes only), signals not used by the rmii mode are reserved when the ethernet controller is multiplexed with the dsi/system bus and rmii mode is selected. these reserved signals can be left unconnected. these rmii reserved signals are not included in table 3-1 , but are indicated in table 3-2 . note: for ethernet signals multiplexed with the gpio/tdm signals, signals not used by the rmii or smii mode can be assigned to their alternate gpio or dedicated function, except for gpio10 and gpio14 . if the ethernet controller is enabled and multiplexed with the gpio signals and smii mode is selected, gpio10 and gpio14 (e21 and f21, respectively) must be left unconnected. these signals are designated as nc (no connect) in table 3-1 and table 3-2 .
msc8122 technical data, rev. 13 3-2 freescale semiconductor packaging figure 3-1. msc8122 package, top view 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 b v dd gnd gnd nmi_ out gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gpio0 v dd v dd gnd cgnd v dd tdo s reset gpio28 hcid1 gnd v dd gnd v dd gnd v dd gnd gnd gpio30 gpio2 gpio1 gpio7 gpio3 gpio5 gpio6 d tdi ee0 ee1 gnd v ddh hcid2 hcid3 gnd v dd gnd v dd gnd v dd v dd gpio31 gpio29 v ddh gpio4 v ddh gnd gpio8 e tck trst tms hreset gpio27 hcid0 gnd v dd gnd v dd gnd v dd gnd gnd v dd gnd gnd gpio9 gpio13 gpio10 gpio1 2 f po reset rst conf nmi ha29 ha22 gnd v dd v dd v dd gnd v dd gnd v dd ethrx_ clk ethtx_ clk gpio20 gpio18 gpio16 gpio11 gpio14 gpio1 9 gha24ha27ha25ha23ha17pwe0 v dd v dd baddr 31 bm0 abb v dd int_ out ethcr s v dd cs1 bctl0 gpio15 gnd gpio17 gpio2 2 hha20 ha28 v dd ha19 test psd cas pgta v dd bm1 artry aack dbb hta v dd tt4 cs4 gpio24 gpio21 v dd v ddh a31 jha18ha26 v dd ha13 gnd psda mux baddr 27 v dd clkin bm2 dbg v dd gnd v dd tt3 psda10 bctl1 gpio23 gnd gpio25 a30 k ha15 ha21 ha16 pwe3 pwe1 poe baddr 30 res. gnd gnd gnd gnd clkout v dd tt2 ale cs2 gnd a26 a29 a28 lha12ha14ha11 v ddh v ddh baddr 28 baddr 29 gnd gnd gnd v ddh gnd gnd cs3 v ddh a27 a25 a22 m hd28 hd31 v ddh gnd gnd gnd v dd v ddh gnd gnd v ddh hb rst v ddh v ddh gnd v ddh a24 a21 n hd26 hd30 hd29 hd24 pwe2 v ddh hwbs 0 hbcs gnd gnd hrds bg hcs cs0 psdwe gpio26 a23 a20 p hd20 hd27 hd25 hd23 hwbs 3 hwbs 2 hwbs 1 hclkin gnd gnd syn v ccsyn gnd gnd ta br tea psd val dp0 v ddh gnd a19 r hd18 v ddh gnd hd22 hwbs 6 hwbs 4 tsz1 tsz3 gbl v dd v dd v dd tt0 dp7 dp6 dp3 ts dp2 a17 a18 a16 t hd17 hd21 hd1 hd0 hwbs 7 hwbs 5 tsz0 tsz2 tbst v dd d16 tt1 d21 d23 dp5 dp4 dp1 d30 gnd a15 a14 u hd16 hd19 hd2 d2 d3 d6 d8 d9 d11 d14 d15 d17 d19 d22 d25 d26 d28 d31 v ddh a12 a13 v hd3 v ddh gndd0d1d4d5d7d10d12d13d18d20gndd24d27d29a8a9a10a11 w hd6 hd5 hd4 gnd gnd v ddh v ddh gnd hdst1 hdst0 v ddh gnd hd40 v ddh hd33 v ddh hd32 gnd gnd a7 a6 y hd7 hd15 v ddh hd9 v dd hd60 hd58 gnd v ddh hd51 gnd v ddh hd43 gnd v ddh gnd hd37 hd34 v ddh a4 a5 aa v dd hd14 hd12 hd10 hd63 hd59 gnd v ddh hd54 hd52 v ddh gnd v ddh hd46 gnd hd42 hd38 hd35 a0 a2 a3 ab gnd hd13 hd11 hd8 hd62 hd61 hd57 hd56 hd55 hd53 hd50 hd49 hd48 hd47 hd45 hd44 hd41 hd39 hd36 a1 v dd top view msc8122
package description msc8122 technical data, rev. 13 freescale semiconductor 3-3 figure 3-2. msc8122 package, bottom view 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 bgnd v dd v dd gpio0 v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd nmi_ out gnd gnd v dd c gpio6 gpio5 gpio3 gpio7 gpio1 gpio2 gpio30 gnd gnd v dd gnd v dd gnd v dd gnd hcid1 gpio28 s reset tdo v dd gnd d gpio8 gnd v ddh gpio4 v ddh gpio29 gpio31 v dd v dd gnd v dd gnd v dd gnd hcid3 hcid2 v ddh gnd ee1 ee0 tdi e gpio12 gpio10 gpio13 gpio9 gnd gnd v dd gnd gnd v dd gnd v dd gnd v dd gnd hcid0 gpio27 hreset tms trst tck f gpio19 gpio14 gpio11 gpio16 gpio18 gpio20 ethtx_ clk ethrx_ clk v dd gnd v dd gnd v dd v dd v dd gnd ha22 ha29 nmi rst conf po reset g gpio22 gpio17 gnd gpio15 bctl0 cs1 v dd ethcr s int_ out v dd abb bm0 baddr 31 v dd v dd pwe0 ha17 ha23 ha25 ha27 ha24 ha31 v ddh v dd gpio21 gpio24 cs4 tt4 v dd hta dbb aack artry bm1 v dd pgta psd cas test ha19 v dd ha28 ha20 j a30 gpio25 gnd gpio23 bctl1 psda10 tt3 v dd gnd v dd dbg bm2 clkin v dd baddr 27 psda mux gnd ha13 v dd ha26 ha18 ka28 a29 a26 gnd cs2 ale tt2 v dd clkout gnd gnd gnd gnd res. baddr 30 poe pwe1 pwe3 ha16 ha21 ha15 la22 a25 a27 v ddh cs3 gnd gnd v ddh gnd gnd gnd baddr 29 baddr 28 v ddh v ddh ha11 ha14 ha12 ma21 a24 v ddh gnd v ddh v ddh hb rst v ddh gnd gnd v ddh v dd gnd gnd gnd v ddh hd31 hd28 n a20 a23 gpio26 psdwe cs0 hcs bg hrds gnd gnd hbcs hwbs 0 v ddh pwe2 hd24 hd29 hd30 hd26 pa19 gnd v ddh dp0 psd va l tea br ta gnd gnd v ccsyn gnd syn gnd hclkin hwbs 1 hwbs 2 hwbs 3 hd23 hd25 hd27 hd20 ra16 a18 a17 dp2 ts dp3 dp6 dp7 tt0 v dd v dd v dd gbl tsz3 tsz1 hwbs 4 hwbs 6 hd22 gnd v ddh hd18 t a14 a15 gnd d30 dp1 dp4 dp5 d23 d21 tt1 d16 v dd tbst tsz2 tsz0 hwbs 5 hwbs 7 hd0 hd1 hd21 hd17 ua13 a12 v ddh d31 d28 d26 d25 d22 d19 d17 d15 d14 d11 d9 d8 d6 d3 d2 hd2 hd19 hd16 v a11 a10 a9 a8 d29 d27 d24 gnd d20 d18 d13 d12 d10 d7 d5 d4 d1 d0 gnd v ddh hd3 wa6 a7 gndgndhd32 v ddh hd33 v ddh hd40 gnd v ddh hdst0 hdst1 gnd v ddh v ddh gnd gnd hd4 hd5 hd6 ya5 a4 v ddh hd34 hd37 gnd v ddh gnd hd43 v ddh gnd hd51 v ddh gnd hd58 hd60 v dd hd9 v ddh hd15 hd7 aa a3 a2 a0 hd35 hd38 hd42 gnd hd46 v ddh gnd v ddh hd52 hd54 v ddh gnd hd59 hd63 hd10 hd12 hd14 v dd ab v dd a1 hd36 hd39 hd41 hd44 hd45 hd47 hd48 hd49 hd50 hd53 hd55 hd56 hd57 hd61 hd62 hd8 hd11 hd13 gnd bottom view msc 81 22
msc8122 technical data, rev. 13 3-4 freescale semiconductor packaging table 3-1. msc8122 signal listing by name signal name location designator signal name location designator a0 aa20 baddr27 j8 a1 ab21 baddr28 l7 a2 aa21 baddr29 l8 a3 aa22 baddr30 k8 a4 y21 baddr31 g10 a5 y22 bctl0 g18 a6 w22 bctl1 j18 a7 w21 bg n16 a8 v19 bnksel0 g11 a9 v20 bnksel1 h10 a10 v21 bnksel2 j11 a11 v22 bm0 g11 a12 u21 bm1 h10 a13 u22 bm2 j11 a14 t22 br p16 a15 t21 chip_id0 b19 a16 r22 chip_id1 c18 a17 r20 chip_id2 c17 a18 r21 chip_id3 d17 a19 p22 clkin j10 a20 n22 clkout k14 a21 m22 cnfgs w3 a22 l22 cs0 n18 a23 n21 cs1 g17 a24 m21 cs2 k18 a25 l21 cs3 l18 a26 k20 cs4 h17 a27 l20 cs5 k16 a28 k22 cs5 j18 a29 k21 cs6 j16 a30 j22 cs7 h16 a31 h22 d0 v5 aack h12 d1 v6 abb g12 d2 u5 ale k17 d3 u6 artry h11 d4 v7
package description msc8122 technical data, rev. 13 freescale semiconductor 3-5 d5 v8 d41 ab18 d6 u7 d42 aa17 d7 v9 d43 y14 d8 u8 d44 ab17 d9 u9 d45 ab16 d10 v10 d46 aa15 d11 u10 d47 ab15 d12 v11 d48 ab14 d13 v12 d49 ab13 d14 u11 d50 ab12 d15 u12 d51 y11 d16 t12 d52 aa11 d17 u13 d53 ab11 d18 v13 d54 aa10 d19 u14 d55 ab10 d20 v14 d56 ab9 d21 t14 d57 ab8 d22 u15 d58 y8 d23 t15 d59 aa7 d24 v16 d60 y7 d25 u16 d61 ab7 d26 u17 d62 ab6 d27 v17 d63 aa6 d28 u18 dack1 g21 d29 v18 dack1 t18 d30 t19 dack2 f22 d31 u19 dack2 r19 d32 w18 dack3 t17 d33 w16 dack4 t16 d34 y19 dbb h13 d35 aa19 dbg j12 d36 ab20 done1 f19 d37 y18 done2 g22 d38 aa18 dp0 p19 d39 ab19 dp1 t18 d40 w14 dp2 r19 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
msc8122 technical data, rev. 13 3-6 freescale semiconductor packaging dp3 r17 ethrxd0 f21 dp4 t17 ethrxd0 w14 dp5 t16 ethrxd1 e22 dp6 r16 ethrxd1 ab18 dp7 r15 ethrxd2 c22 drack1 f19 ethrxd2 aa17 drack2 g22 ethrxd3 c21 dreq1 e6 ethrxd3 y14 dreq1 g19 ethsync e22 dreq1 p19 ethsync_in f15 dreq2 c6 ethtx_clk f16 dreq2 f18 ethtx_en d17 dreq2 r17 ethtx_en aa10 dreq3 r16 ethtx_er d19 dreq4 r15 ethtx_er ab10 dsi64 u4 ethtxd f20 dsisync t4 ethtxd0 b19 ee0 d3 ethtxd0 aa15 ee1 d4 ethtxd1 c18 ethclock f16 ethtxd1 ab15 ethcol d22 ethtxd2 c20 ethcol y7 ethtxd2 ab14 ethcrs g15 ethtxd3 c19 ethcrs_dv e21 ethtxd3 ab13 ethcrs_dv ab9 ext_bg2 t18 ethmdc e20 ext_bg3 t16 ethmdc y8 ext_br2 p19 ethmdio e19 ext_br3 r17 ethmdio aa7 ext_dbg2 r19 ethref_clk f16 ext_dbg3 t17 ethrx_clk f15 gbl r10 ethrx_dv e21 gnd b4 ethrx_dv ab9 gnd b5 ethrx_er f20 gnd b7 ethrx_er ab8 gnd b9 ethrxd g15 gnd b11 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
package description msc8122 technical data, rev. 13 freescale semiconductor 3-7 gnd b13 gnd l14 gnd b15 gnd l16 gnd b17 gnd l17 gnd b22 gnd m5 gnd c2 gnd m6 gnd c8 gnd m7 gnd c10 gnd m10 gnd c12 gnd m14 gnd c14 gnd m19 gnd c15 gnd n10 gnd d5 gnd n14 gnd d9 gnd p10 gnd d11 gnd p13 gnd d13 gnd p14 gnd d21 gnd p21 gnd e8 gnd r4 gnd e10 gnd t20 gnd e12 gnd v4 gnd e14 gnd v15 gnd e15 gnd w5 gnd e17 gnd w6 gnd e18 gnd w9 gnd f7 gnd w13 gnd f11 gnd w19 gnd f13 gnd w20 gnd g20 gnd y9 gnd j6 gnd y12 gnd j14 gnd y15 gnd j20 gnd y17 gnd k10 gnd aa8 gnd k11 gnd aa13 gnd k12 gnd aa16 gnd k13 gnd ab2 gnd k19 gnd syn p11 gnd l9 gpio0 b19 gnd l10 gpio1 c18 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
msc8122 technical data, rev. 13 3-8 freescale semiconductor packaging gpio2 c17 ha13 j5 gpio3 c20 ha14 l3 gpio4 d19 ha15 k2 gpio5 c21 ha16 k4 gpio6 c22 ha17 g6 gpio7 c19 ha18 j2 gpio8 d22 ha19 h5 gpio9 e19 ha20 h2 gpio10 e21 ha21 k3 gpio11 f20 ha22 f6 gpio12 e22 ha23 g5 gpio13 e20 ha24 g2 gpio14 f21 ha25 g4 gpio15 g19 ha26 j3 gpio16 f19 ha27 g3 gpio17 g21 ha28 h3 gpio18 f18 ha29 f5 gpio19 f22 hbcs n9 gpio20 f17 hbrst m16 gpio21 h19 hcid0 e7 gpio22 g22 hcid1 c7 gpio23 j19 hcid2 d7 gpio24 h18 hcid3 d8 gpio25 j21 hclkin p9 gpio26 n20 hcs n17 gpio27 e6 hd0 t5 gpio28 c6 hd1 t4 gpio29 d17 hd2 u4 gpio30 c16 hd3 v2 gpio31 d16 hd4 w4 ha7 r14 hd5 w3 ha8 d8 hd6 w2 ha9 w11 hd7 y2 ha10 w10 hd8 ab5 ha11 l4 hd9 y5 ha12 l2 hd10 aa5 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
package description msc8122 technical data, rev. 13 freescale semiconductor 3-9 hd11 ab4 hd47 ab15 hd12 aa4 hd48 ab14 hd13 ab3 hd49 ab13 hd14 aa3 hd50 ab12 hd15 y3 hd51 y11 hd16 u2 hd52 aa11 hd17 t2 hd53 ab11 hd18 r2 hd54 aa10 hd19 u3 hd55 ab10 hd20 p2 hd56 ab9 hd21 t3 hd57 ab8 hd22 r5 hd58 y8 hd23 p5 hd59 aa7 hd24 n5 hd60 y7 hd25 p4 hd61 ab7 hd26 n2 hd62 ab6 hd27 p3 hd63 aa6 hd28 m2 hdbe0 n8 hd29 n4 hdbe1 p8 hd30 n3 hdbe2 p7 hd31 m3 hdbe3 p6 hd32 w18 hdbe4 r7 hd33 w16 hdbe5 t7 hd34 y19 hdbe6 r6 hd35 aa19 hdbe7 t6 hd36 ab20 hdbs 0 n8 hd37 y18 hdbs1 p8 hd38 aa18 hdbs2 p7 hd39 ab19 hdbs3 p6 hd40 w14 hdbs4 r7 hd41 ab18 hdbs5 t7 hd42 aa17 hdbs6 r6 hd43 y14 hdbs7 t6 hd44 ab17 hdst0 w11 hd45 ab16 hdst1 w10 hd46 aa15 hrde n15 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
msc8122 technical data, rev. 13 3-10 freescale semiconductor packaging hrds n15 irq5 h13 hreset e5 irq5 l8 hrw n15 irq5 t16 hta h14 irq6 c17 hwbe0 n8 irq6 d22 hwbe1 p8 irq6 r16 hwbe2 p7 irq7 e19 hwbe3 p6 irq7 g14 hwbe4 r7 irq7 r15 hwbe5 t7 irq8 e21 hwbe6 r6 irq9 f20 hwbe7 t6 irq10 e22 hwbs0 n8 irq11 e20 hwbs1 p8 irq12 f21 hwbs2 p7 irq13 j19 hwbs3 p6 irq14 h18 hwbs4 r7 irq15 j21 hwbs5 t7 modck1 v2 hwbs6 r6 modck2 w4 hwbs7 t6 nc e21 int_out g14 nc f21 irq1 c20 nmi f4 irq1 r10 nmi_out b6 irq1 t18 pbs0 g7 irq2 d19 pbs1 k6 irq2 k8 pbs2 n6 irq2 r19 pbs3 k5 irq3 c21 pbs4 r7 irq3 g10 pbs5 t7 irq3 r17 pbs6 r6 irq4 b19 pbs7 t6 irq4 c22 pgpl0 j17 irq4 g12 pgpl1 n19 irq4 t17 pgpl2 k7 irq5 c18 pgpl3 h7 irq5 c19 pgpl4 h8 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
package description msc8122 technical data, rev. 13 freescale semiconductor 3-11 pgpl5 j7 tc0 g11 pgta h8 tc1 h10 poe k7 tc2 j11 poreset f2 tck e2 ppbs h8 tdi d2 psda10 j17 tdm0rclk j21 psdamux j7 tdm0rdat n20 psdcas h7 tdm0rsyn h18 psddqm0 g7 tdm0tclk g22 psddqm1 k6 tdm0tdat j19 psddqm2 n6 tdm0tsyn h19 psddqm3 k5 tdm1rclk f22 psddqm4 r7 tdm1rdat f17 psddqm5 t7 tdm1rsyn f18 psddqm6 r6 tdm1tclk f19 psddqm7 t6 tdm1tdat g21 psdras k7 tdm1tsyn g19 psdval p18 tdm2rclk e20 psdwe n19 tdm2rdat f21 pwe0 g7 tdm2rsyn e22 pwe1 k6 tdm2tclk e21 pwe2 n6 tdm2tdat f20 pwe3 k5 tdm2tsyn e19 pwe4 r7 tdm3rclk c19 pwe5 t7 tdm3rdat d22 pwe6 r6 tdm3rsyn c22 pwe7 t6 tdm3tclk d19 pupmwait h8 tdm3tdat c21 reserved k9 tdm3tsyn c20 rstconf f3 tdo c4 scl d16 tea p17 sda c16 test h6 sreset c5 timer0 c18 swte t5 timer1 c17 ta p15 timer2 c16 tbst t10 timer3 d16 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
msc8122 technical data, rev. 13 3-12 freescale semiconductor packaging tmclk c16 v dd f8 tms e4 v dd f9 trst e3 v dd f10 ts r18 v dd f12 tsz0 t8 v dd f14 tsz1 r8 v dd g8 tsz2 t9 v dd g9 tsz3 r9 v dd g13 tt0 r14 v dd g16 tt1 t13 v dd h4 tt2 k16 v dd h9 tt3 j16 v dd h15 tt4 h16 v dd h20 urxd e6 v dd j4 utxd c6 v dd j9 v ccsyn p12 v dd j13 v dd b8 v dd j15 v dd b10 v dd k15 v dd b12 v dd m8 v dd b14 v dd r11 v dd b16 v dd r12 v dd b18 v dd r13 v dd b20 v dd t11 v dd b21 v dd y6 v dd c3 v dd aa2 v dd c9 v dd b3 v dd c11 v dd ab22 v dd c13 v ddh d6 v dd d10 v ddh d18 v dd d12 v ddh d20 v dd d14 v ddh h21 v dd d15 v ddh l5 v dd e9 v ddh l6 v dd e11 v ddh l15 v dd e13 v ddh l19 v dd e16 v ddh m4 table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
package description msc8122 technical data, rev. 13 freescale semiconductor 3-13 v ddh m9 v ddh w12 v ddh m15 v ddh w15 v ddh m17 v ddh w17 v ddh m18 v ddh y4 v ddh m20 v ddh y10 v ddh n7 v ddh y13 v ddh p20 v ddh y16 v ddh r3 v ddh y20 v ddh u20 v ddh aa9 v ddh v3 v ddh aa12 v ddh w7 v ddh aa14 v ddh w8 note: this table lists every signal name. because many signal s are multiplexed, an individual ball designator number may be lis ted several times. table 3-1. msc8122 signal listing by name (continued) signal name location designator signal name location designator
msc8122 technical data, rev. 13 3-14 freescale semiconductor packaging table 3-2. msc8122 signal listing by ball designator des. signal name des. signal name b3 v dd c18 gpio1/timer0/chip_id1/ irq5 /ethtxd1 b4 gnd c19 gpio7/tdm3rclk/ irq5 /ethtxd3 b5 gnd c20 gpio3/tdm3tsyn/ irq1 /ethtxd2 b6 nmi_out c21 gpio5/tdm3tdat/ irq3 /ethrxd3 b7 gnd c22 gpio6/tdm3rsyn/ irq4 /ethrxd2 b8 v dd d2 tdi b9 gnd d3 ee0 b10 v dd d4 ee1 b11 gnd d5 gnd b12 v dd d6 v ddh b13 gnd d7 hcid2 b14 v dd d8 hcid3/ha8 b15 gnd d9 gnd b16 v dd d10 v dd b17 gnd d11 gnd b18 v dd d12 v dd b19 gpio0/chip_id0/ irq4 /ethtxd0 d13 gnd b20 v dd d14 v dd b21 v dd d15 v dd b22 gnd d16 gpio31/timer3/scl c2 gnd d17 gpio29/chip_id3/ethtx_en c3 v dd d18 v ddh c4 tdo d19 gpio4/tdm3tclk/ irq2 /ethtx_er c5 sreset d20 v ddh c6 gpio28/utxd/dreq2 d21 gnd c7 hcid1 d22 gpio8/tdm3rdat/ irq6 /ethcol c8 gnd e2 tck c9 v dd e3 trst c10 gnd e4 tms c11 v dd e5 hreset c12 gnd e6 gpio27/urxd/dreq1 c13 v dd e7 hcid0 c14 gnd e8 gnd c15 gnd e9 v dd c16 gpio30/timer2/tmclk/sda e10 gnd c17 gpio2/timer1/chip_id2/ irq6 e11 v dd
package description msc8122 technical data, rev. 13 freescale semiconductor 3-15 e12 gnd g6 ha17 e13 v dd g7 pwe0 / psddqm0 / pbs0 e14 gnd g8 v dd e15 gnd g9 v dd e16 v dd g10 irq3 /baddr31 e17 gnd g11 bm0/tc0/bnksel0 e18 gnd g12 abb / irq4 e19 gpio9/tdm2tsyn/ irq7 /ethmdio g13 v dd e20 gpio13/tdm2rclk/ irq11 /ethmdc g14 irq7 / int_out e21 gpio10/tdm2tclk/ irq8 /ethrx_dv/ethcrs_dv/nc g15 ethcrs/ethrxd e22 gpio12/tdm2rsyn/ irq10 /ethrxd1/ethsync g16 v dd f2 poreset g17 cs1 f3 rstconf g18 bctl0 f4 nmi g19 gpio15/tdm1tsyn/dreq1 f5 ha29 g20 gnd f6 ha22 g21 gpio17/tdm1tdat/ dack1 f7 gnd g22 gpio22/tdm0tclk/ done2 / drack2 f8 v dd h2 ha20 f9 v dd h3 ha28 f10 v dd h4 v dd f11 gnd h5 ha19 f12 v dd h6 test f13 gnd h7 psdcas /pgpl3 f14 v dd h8 pgta /pupmwait/pgpl4/ ppbs f15 ethrx_clk/ethsync_in h9 v dd f16 ethtx_clk/ethref_clk/ethclock h10 bm1/tc1/bnksel1 f17 gpio20/tdm1rdat h11 artry f18 gpio18/tdm1rsyn/dreq2 h12 aack f19 gpio16/tdm1tclk/ done1 / drack1 h13 dbb / irq5 f20 gpio11/tdm2tdat/ irq9 /ethrx_er/ethtxd h14 hta f21 gpio14/tdm2rdat/ irq12 /ethrxd0/nc h15 v dd f22 gpio19/tdm1rclk/ dack2 h16 tt4/ cs7 g2 ha24 h17 cs4 g3 ha27 h18 gpio24/tdm0rsyn/ irq14 g4 ha25 h19 gpio21/tdm0tsyn g5 ha23 h20 v dd table 3-2. msc8122 signal listing by ball designator (continued) des. signal name des. signal name
msc8122 technical data, rev. 13 3-16 freescale semiconductor packaging h21 v ddh k15 v dd h22 a31 k16 tt2/ cs5 j2 ha18 k17 ale j3 ha26 k18 cs2 j4 v dd k19 gnd j5 ha13 k20 a26 j6 gnd k21 a29 j7 psdamux/pgpl5 k22 a28 j8 baddr27 l2 ha12 j9 v dd l3 ha14 j10 clkin l4 ha11 j11 bm2/tc2/bnksel2 l5 v ddh j12 dbg l6 v ddh j13 v dd l7 baddr28 j14 gnd l8 irq5 /baddr29 j15 v dd l9 gnd j16 tt3/ cs6 l10 gnd j17 psda10/pgpl0 l14 gnd j18 bctl1 / cs5 l15 v ddh j19 gpio23/tdm0tdat/ irq13 l16 gnd j20 gnd l17 gnd j21 gpio25/tdm0rclk/ irq15 l18 cs3 j22 a30 l19 v ddh k2 ha15 l20 a27 k3 ha21 l21 a25 k4 ha16 l22 a22 k5 pwe3 / psddqm3 / pbs3 m2 hd28 k6 pwe1 / psddqm1 / pbs1 m3 hd31 k7 poe / psdras /pgpl2 m4 v ddh k8 irq2 /baddr30 m5 gnd k9 reserved m6 gnd k10 gnd m7 gnd k11 gnd m8 v dd k12 gnd m9 v ddh k13 gnd m10 gnd k14 clkout m14 gnd table 3-2. msc8122 signal listing by ball designator (continued) des. signal name des. signal name
package description msc8122 technical data, rev. 13 freescale semiconductor 3-17 m15 v ddh p12 v ccsyn m16 hbrst p13 gnd m17 v ddh p14 gnd m18 v ddh p15 ta m19 gnd p16 br m20 v ddh p17 tea m21 a24 p18 psdval m22 a21 p19 dp0/dreq1/ ext_br2 n2 hd26 p20 v ddh n3 hd30 p21 gnd n4 hd29 p22 a19 n5 hd24 r2 hd18 n6 pwe2 / psddqm2 / pbs2 r3 v ddh n7 v ddh r4 gnd n8 hwbs0 / hdbs0 / hwbe0 / hdbe0 r5 hd22 n9 hbcs r6 hwbs6 / hdbs6 / hwbe6 / hdbe6 / pwe6 / psddqm6 / pbs6 n10 gnd r7 hwbs4 / hdbs4 / hwbe4 / hdbe4 / pwe4 / psddqm4 / pbs4 n14 gnd r8 tsz1 n15 hrds /hrw/ hrde r9 tsz3 n16 bg r10 irq1 / gbl n17 hcs r11 v dd n18 cs0 r12 v dd n19 psdwe /pgpl1 r13 v dd n20 gpio26/tdm0rdat r14 tt0/ha7 n21 a23 r15 irq7 /dp7/dreq4 n22 a20 r16 irq6 /dp6/dreq3 p2 hd20 r17 irq3 /dp3/dreq2/ ext_br3 p3 hd27 r18 ts p4 hd25 r19 irq2 /dp2/ dack2 / ext_dbg2 p5 hd23 r20 a17 p6 hwbs3 / hdbs3 / hwbe3 / hdbe3 r21 a18 p7 hwbs2 / hdbs2 / hwbe2 / hdbe2 r22 a16 p8 hwbs1 / hdbs1 / hwbe1 / hdbe1 t2 hd17 p9 hclkin t3 hd21 p10 gnd t4 hd1/dsisync p11 gnd syn t5 hd0/swte table 3-2. msc8122 signal listing by ball designator (continued) des. signal name des. signal name
msc8122 technical data, rev. 13 3-18 freescale semiconductor packaging t6 hwbs7 / hdbs7 / hwbe7 / hdbe7 / pwe7 / psddqm7 / pbs7 u21 a12 t7 hwbs5 / hdbs5 / hwbe5 / hdbe5 / pwe5 / psddqm5 / pbs5 u22 a13 t8 tsz0 v2 hd3/modck1 t9 tsz2 v3 v ddh t10 tbst v4 gnd t11 v dd v5 d0 t12 d16 v6 d1 t13 tt1 v7 d4 t14 d21 v8 d5 t15 d23 v9 d7 t16 irq5 /dp5/ dack4 / ext_bg3 v10 d10 t17 irq4 /dp4/ dack3 / ext_dbg3 v11 d12 t18 irq1 /dp1/ dack1 / ext_bg2 v12 d13 t19 d30 v13 d18 t20 gnd v14 d20 t21 a15 v15 gnd t22 a14 v16 d24 u2 hd16 v17 d27 u3 hd19 v18 d29 u4 hd2/dsi64 v19 a8 u5 d2 v20 a9 u6 d3 v21 a10 u7 d6 v22 a11 u8 d8 w2 hd6 u9 d9 w3 hd5/cnfgs u10 d11 w4 hd4/modck2 u11 d14 w5 gnd u12 d15 w6 gnd u13 d17 w7 v ddh u14 d19 w8 v ddh u15 d22 w9 gnd u16 d25 w10 hdst1/ha10 u17 d26 w11 hdst0/ha9 u18 d28 w12 v ddh u19 d31 w13 gnd u20 v ddh w14 hd40/d40/ethrxd0 table 3-2. msc8122 signal listing by ball designator (continued) des. signal name des. signal name
package description msc8122 technical data, rev. 13 freescale semiconductor 3-19 w15 v ddh aa9 v ddh w16 hd33/d33/reserved aa10 hd54/d54/ethtx_en w17 v ddh aa11 hd52/d52 w18 hd32/d32/reserved aa12 v ddh w19 gnd aa13 gnd w20 gnd aa14 v ddh w21 a7 aa15 hd46/d46/ethtxt0 w22 a6 aa16 gnd y2 hd7 aa17 hd42/d42/ethrxd2/reserved y3 hd15 aa18 hd38/d38/reserved y4 v ddh aa19 hd35/d35/reserved y5 hd9 aa20 a0 y6 v dd aa21 a2 y7 hd60/d60/ethcol/reserved aa22 a3 y8 hd58/d58/ethmdc ab2 gnd y9 gnd ab3 hd13 y10 v ddh ab4 hd11 y11 hd51/d51 ab5 hd8 y12 gnd ab6 hd62/d62 y13 v ddh ab7 hd61/d61 y14 hd43/d43/ethrxd3/reserved ab8 hd57/d57/ethrx_er y15 gnd ab9 hd56/d56/ethrx_dv/ethcrs_dv y16 v ddh ab10 hd55/d55/ethtx_er/reserved y17 gnd ab11 hd53/d53 y18 hd37/d37/reserved ab12 hd50/d50 y19 hd34/d34/reserved ab13 hd49/d49/ethtxd3/reserved y20 v ddh ab14 hd48/d48/ethtxd2/reserved y21 a4 ab15 hd47/d47/ethtxd1 y22 a5 ab16 hd45/d45 aa2 v dd ab17 hd44/d44 aa3 hd14 ab18 hd41/d41/ethrxd1 aa4 hd12 ab19 hd39/d39/reserved aa5 hd10 ab20 hd36/d36/reserved aa6 hd63/d63 ab21 a1 aa7 hd59/d59/ethmdio ab22 v dd aa8 gnd table 3-2. msc8122 signal listing by ball designator (continued) des. signal name des. signal name
msc8122 technical data, rev. 13 3-20 freescale semiconductor packaging 3.2 msc8122 package mechanical drawing figure 3-3. msc8122 mechanical information, 431-pin fc-pbga package notes: 1. all dimensions in millimeters. 2. dimensioning and tolerancing per asme y14.5m?1994. 3. features are symmetrical abou t the package center lines unless dimensioned otherwise. 4. maximum solder ball diameter measured parallel to datum a. 5. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 6. parallelism measurement shall exclude any effect of mark on top surface of package. 7. capacitors may not be present on all devices. 8. caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 9. fc cbga (ceramic) package code: 5238. fc pbga (plastic) package code: 5263. 10.pin 1 indicator can be in the form of number 1 marking or an ?l? shape marking.
msc8122 technical data, rev. 13 freescale semiconductor 4-1 design considerations 4 the following sections discuss areas to consider when the msc8122 device is designed into a system. 4.1 start-up sequencing recommendations use the following guidelines for start-up and power-down sequences: ? assert poreset and trst before applying power and keep the signals driven low until the power reaches the required minimum power levels. this can be implemented via weak pull-down resistors. ? clkin can be held low or allowed to toggle during the beginning of the power-up sequence. however, clkin must start toggling before the deassertion of poreset and after both power supplies have reached nominal voltage levels. ? if possible, bring up v dd / v ccsyn and v ddh together. if it is not possible, raise v dd / v ccsyn first and then bring up v ddh . v ddh should not exceed v dd / v ccsyn until v dd / v ccsyn reaches its nominal voltage level. similarly, bring both voltage levels down together. if that is not possible reverse the power-up sequence, with v ddh going down first and then v dd / v ccsyn . note: this recommended power sequencing for the msc8122 is different from the msc8102. external voltage applied to any input line must not exceed the i/o supply v ddh by more than 0.8 v at any time, including during power-up. some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. this is an acceptable exception to the rule. however, each such input can draw up to 80 ma per input pin per device in the system during start-up. after power-up, v ddh must not exceed v dd / v ccsyn by more than 2.6 v. 4.2 power supply design considerations when used as a drop-in replacement in msc8102 applications or when implementing a new design, use the guidelines described in migrating designs from the msc8102 to the msc8122 (an2716) and the msc8122 design checklist (an2787) for optimal system performance. msc8122 and msc8126 power circuit design recommendations and examples (an2937) provides detailed design information. figure 4-1 shows the recommended power decoupling circuit for the core power supply. the voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. the voltage on the package pins should not drop below the minimum specified voltage level even for a very short spikes. this can be achieved by using the following guidelines: ? for the core supply, use a voltage regulator rated at 1.2 v with nominal rating of at least 3 a. this rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings.
msc8122 technical data, rev. 13 4-2 freescale semiconductor design considerations ? decouple the supply using low-esr capacitors mounted as close as possible to the socket. figure 4-1 shows three capacitors in parallel to reduce the resistance. three capacitors is a recommended minimum number. if possible, mount at least one of the capacitors directly below the msc8122 device. each v cc and v dd pin on the msc8122 device should have a low-impedance path to the board power supply. similarly, each gnd pin should have a low-impedance path to the ground plane. the power supply pins drive distinct groups of logic on the chip. the v cc power supply should have at least four 0.1 f by-pass capacitors to ground located as closely as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc , v dd , and gnd should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the msc8122 have fast rise and fall times. pcb trace interconnection length should be minimized to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pcb trace lengths of six inches are recommended. for the dsi control signals in synchronous mode, ensure that the layout supports the dsi ac timing requirements and minimizes any signal crosstalk. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pcb traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc , v dd , and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. there is one pair of pll supply pins: v ccsyn - gnd syn . to ensure internal clock stability, filter the power to the v ccsyn input with a circuit similar to the one in figure 4-2 . for optimal noise filtering, place the circuit as close as possible to v ccsyn . the 0.01-f capacitor should be closest to v ccsyn , followed by the 10-f capacitor, the 10-nh inductor, and finally the 10- resistor to v dd . these traces should be kept short and direct. provide an extremely low impedance path to the ground plane for gnd syn . bypass gnd syn to v ccsyn by a 0.01-f capacitor located as close as possible to the chip package. for best results, place this capacitor on the backside of the pcb aligned with the depopulated void on the msc8122 located in the square defined by positions, l11, l12, l13, m11, m12, m13, n11, n12, and n13. figure 4-1. core power supply decoupling figure 4-2. v ccsyn bypass + - power supply or voltage regulator high frequency capacitors (very low esr and esl) bulk/tantalum capacitors with low esr and esl msc8122 maximum ir drop of 15 mv at 1 a note : use at least three capacitors. l max = 2 cm one 0.01 f capacitor for every 3 core supply (i min = 3 a) pads. 1.2 v each capacitor must be at least 150 f. v dd 0.01 f 10 f v ccsyn 10 10nh
connectivity guidelines msc8122 technical data, rev. 13 freescale semiconductor 4-3 4.3 connectivity guidelines unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to v ddh or gnd , except for the following: ? if the dsi is unused (ddr[dsidis] is set), hcs and hbcs must pulled up and all the rest of the dsi signals can be disconnected. ? when the dsi uses synchronous mode, hta must be pulled up. in asynchronous mode, hta should be pulled either up or down, depending on design requirements. ? hdst can be disconnected if the dsi is in big-endian mode, or if the dsi is in little-endian mode and the dcr[dsrfa] bit is set. ? when the dsi is in 64-bit data bus mode and dcr[bem] is cleared, pull up hwbs[1?3] / hdbs[1?3] / hwbe[1?3] / hdbe[1?3] and hwbs[4?7] / hdbs[4?7] / hwbe[4?7] / hdbe[4?7] / pwe[4?7] / psddqm[4?7] / pbs[4?7] . ? when the dsi is in 32-bit data bus mode and dcr[bem] is cleared, hwbs[1?3] / hdbs[1?3] / hwbe[1?3] / hdbe[1?3] must be pulled up. ? when the dsi is in asynchronous mode, hbrst and hclkin should either be disconnected or pulled up. ? the following signals must be pulled up: hreset , sreset , artry , ta , tea , psdval , and aack . ? in single-master mode (bcr[ebm] = 0) with internal arbitration (ppc_acr[earb] = 0): ? bg , dbg , and ts can be left unconnected. ? ext_bg[2?3] , ext_dbg[2?3] , and gbl can be left unconnected if they are multiplexed to the system bus functionality. for any other functionality, connect the signal lines based on the multiplexed functionality. ? br must be pulled up. ? ext_br[2?3] must be pulled up if multiplexed to the system bus functionality. ? if there is an external bus master (bcr[ebm] = 1): ? br , bg , dbg , and ts must be pulled up. ? ext_br[2?3] , ext_bg[2?3] , and ext_dbg[2?3] must be pulled up if multiplexed to the system bus functionality. ? in single-master mode, abb and dbb can be selected as irq inputs and be connected to the non-active value. in other modes, they must be pulled up. note: the msc8122 does not support dll-enabled mode. for the following two clock schemes, ensure that the dll is disabled (that is, the dlldis bit in the hard reset configuration word is set). ? if no system synchronization is required (for example, the design does not use sdram), you can use any of the available clock modes. ?in the clkin synchronization mode, use the following connections: ? connect the oscillator output through a buffer to clkin . ? connect the clkin buffer output to the slave device (for example, sdram) making sure that the delay path between the clock buffer to the msc8122 and the sdram is equal (that is, has a skew less than 100 ps). ? valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
msc8122 technical data, rev. 13 4-4 freescale semiconductor design considerations ?in clkout synchronization mode (for 1.2 v devices), clkout is the main clock to sdram. use the following connections: ? connect the oscillator output through a buffer to clkin . ? connect clkout through a zero-delay buffer to the slave device (for example, sdram) using the following guidelines: ? the maximum delay between the slave and clkout must not exceed 0.7 ns. ? the maximum load on clkout must not exceed 10 pf. ? use a zero-delay buffer with a jitter less than 0.3 ns. ? all clock modes are valid in this clock scheme. note: see the clock chapter in the msc8122 reference manual for details. ? if the 60x-compatible system bus is not used and siumcr[pbse] is set, ppbs can be disconnected. otherwise, it should be pulled up. ? the following signals: swte, dsisync, dsi64, modck[1?2], cnfgs, chipid[0?3] , rstconf and bm[0?2] are used to configure the msc8122 and are sampled on the deassertion of the poreset signal. therefore, they should be tied to gnd or v ddh or through a pull-down or a pull-up resistor until the deassertion of the poreset signal. ? when they are used, int_out (if siumcr[intodc] is cleared), nmi_out , and irqxx (if not full drive) signals must be pulled up. ? when the ethernet controller is enabled and the smii mode is selected, gpio10 and gpio14 must not be connected externally to any signal line. note: for details on configuration, see the msc8122 user?s guide and msc8122 reference manual . for additional information, refer to the msc8122 design checklist (an2787). 4.4 external sdram selection the external bus speed implemented in a system determines the speed of the sdram used on that bus. however, because of differences in timing characteristics among various sdram manufacturers, you may have use a faster speed rated sdram to assure efficient data transfer across the bus. for example, for 166 mhz operation, you may have to use 183 or 200 mhz sdram. always perform a detailed timing analysis using the msc8122 bus timing values and the manufacturer specifications for the sdram to ensure correct operation within your system design. the output delay listed in sdram specifications is usually given for a load of 30 pf. scale the number to your specific board load using the typical scaling number provided by the sdram manufacturer.
thermal considerations msc8122 technical data, rev. 13 freescale semiconductor 4-5 4.5 thermal considerations an estimation of the chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (r ja p d ) equation 1 where t a = ambient temperature near the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = p int + p i/o = power dissipation in the package (w) p int = i dd v dd = internal power dissipation (w) p i/o = power dissipated from device on output pins (w) the power dissipation values for the msc8122 are listed in table 2-3 . the ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. the junction-to-ambient thermal resistances are jedec standard values that provide a quick and easy estimation of thermal performance. there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. the value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (pcb). the value obtained using a single layer board is appropriate for tightly packed pcb configurations. the value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 w/cm 2 with natural convection) and well separated components. based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. if t j appears to be too high, either lower the ambient temperature or the power dissipation of the chip. you can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. the msc8122 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. use the following equation to determine t j : t j = t t + ( ja p d ) equation 2 where t t = thermocouple (or infrared) temperature on top of the package ( c) ja = thermal characterization parameter ( c/w) p d = power dissipation in the package (w) note: see msc8102, msc8122, and msc8126 thermal management design guidelines (an2601/d).
msc8122 rev. 13 10/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there ar e no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale, the freescale logo, and codewarrior are trademarks of freescale semiconductor, inc. starcore is a licensed trademark of starcore llc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004, 2006. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 mnchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-m eguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t. hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com ordering information consult a freescale semiconductor sales office or authorized distributor to determine product availability and place an order. part package type core voltage operating temperature core frequency (mhz) order number lead-free lead-bearing msc8122 flip chip plastic ball grid array (fc-pbga) 1.1 v ?40 to 105c 300 msc8122tvt4800v msc8122tmp4800v 400 msc8122tvt6400v msc8122tmp6400v 1.2 v ?40 to 105c 400 msc8122tvt6400 msc8122tmp6400 0 to 90c 500 msc8122vt8000 MSC8122MP8000

▲Up To Search▲

Price & Availability of MSC8122MP8000

	To Download MSC8122MP8000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .